PI6CG338Q2ZLWEX

Overview

The PI6CG338Q2ZLWEX is an 8-output PCIe Gen 6 clock generator designed for automotive applications. It accepts a 25 MHz crystal or CMOS input to generate eight differential low-power HCSL outputs at 100 MHz with on-chip termination. The device features very-low jitter performance compliant with PCIe Gen 1 through Gen 6 specifications, including RMS jitter below 0.04 ps for Gen 6 common clock. It operates within a supply voltage range of 3.135 V to 3.465 V and supports an ambient temperature range from -40°C to +105°C. The component is housed in a 48-contact 6x6 mm VFQFN package.

Feature Summary

• Generates eight differential low-power HCSL outputs with integrated on-chip termination
• Supports selectable spread-spectrum options (0%, -0.25%, -0.5%) via strapping pins or SMBus
• Programmable slew rate and output amplitude for each individual output channel
• AEC-Q100 qualified for Automotive Grade 2 applications

Applications

• PCIe Gen 6 reference clock generation
• Automotive infotainment systems
• Advanced driver-assistance systems (ADAS)
• Automotive networking modules

Procurement Notes

Verify the specific suffix ZLWEX corresponds to the 48-contact 6x6mm VFQFN exposed pad package. Confirm that the ordering code includes the required automotive qualification and RoHS compliance status as specified by Diodes Incorporated. Ensure compatibility with the intended PCB layout for the QFN footprint.

Selection Notes

Select this component when designing for PCIe Gen 6 requirements necessitating ultra-low jitter performance. The device requires a 25 MHz reference source and provides configurable output parameters via SMBus. Consider the 3.3V nominal supply requirement and the availability of individual output enable controls for power management optimization.

Part Context

This part belongs to the PI6CG338Q family of clock generators specifically engineered for high-speed serial link applications. It serves as a critical timing source for downstream receivers requiring precise clock synchronization. The device integrates proprietary PLL technology to minimize phase noise while maintaining compliance with evolving PCIe standards.

Replacement Considerations

Public confirmed substitute part numbers are not available.