PI6PCIEB24ZDE

Overview

The PI6PCIEB24ZDE is a 1:4 PCI Express® 2.0 compliant differential clock driver manufactured by Diodes Incorporated (formerly Pericom). It distributes a single differential input clock to four differential output pairs using a zero-delay PLL. The device operates at 100 MHz with a 3.3V supply, delivering low skew (<50ps) and cycle-to-cycle jitter (<50ps). Additive RMS phase jitter is less than 1 ps. It features programmable output current via an external resistor, power-down control, and individual output enable pins for each bank.

Feature Summary

• PCIe 2.0 Compliant: Includes phase jitter filtering for PCIe GenII applications.
• Low Jitter Performance: Cycle-to-cycle jitter <50ps; additive RMS phase jitter <1ps.
• Flexible Control: Features PWRDWN# for power down, PLL/BYPASS# for mode selection, and OE_0/OE_3 for independent output bank enabling.
• Current Programmability: Differential output current is set by an external IREF resistor.

Applications

• PCI Express 2.0 System Clock Distribution
• High-speed server and workstation motherboard designs
• Network equipment requiring low-jitter clock buffering

Procurement Notes

Verify the package code ZD corresponds to the 20-pin TQFN (4.0mm x 4.0mm). Confirm RoHS compliance through the 'E' suffix in the ordering code. Ensure the specific revision matches the datasheet PS9070A dated 09/01/10 for accurate electrical characteristics.

Selection Notes

Select this component when a 1:4 differential clock buffer with strict PCIe 2.0 jitter requirements is needed. It requires a 3.3V supply and an external resistor for IREF setting. Consider bypass mode if PLL functionality is not required for system testing.

Part Context

This part belongs to the PI6PCIE series of high-speed clock drivers designed specifically for PCI Express standards. It serves as a buffer between a clock synthesizer (like the PI6C410) and multiple PCIe endpoints or switches.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Verify pinout compatibility and electrical specifications before considering alternative vendors.

FAQ

How is the output current configured?

The differential output current is determined by an external resistor connected to the IREF pin. For example, a 475Ω resistor sets the nominal current.

What is the function of the PLL/BYPASS# pin?

When HIGH, the internal PLL is enabled for normal operation. When LOW, the PLL is bypassed, allowing the input clock to pass directly to the outputs with a propagation delay of 2.5ns to 6.5ns.

How does the device behave during power down?

Asserting PWRDWN# Low puts the device in power down mode, where 2xIREF current flows through the OUT pins, resulting in a low state.