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Product Detailed Parameters
- Description：JFET N-CH 40V TO92
- Series：PN4119
- Mfr：Linear Integrated Systems, Inc.
- Package：Tape & Reel (TR),Cut Tape (CT)
- FET Type：N-Channel
- Voltage - Breakdown (V(BR)GSS)：40 V
- Drain to Source Voltage (Vdss)：-
- Current - Drain (Idss) @ Vds (Vgs=0)：200 µA @ 10 V
- Current Drain (Id) - Max：-
- Voltage - Cutoff (VGS off) @ Id：2 V @ 1 nA
- Input Capacitance (Ciss) (Max) @ Vds：3pF @ 10V
- Resistance - RDS(On)：-
- Power - Max：300 mW
- Operating Temperature：-
- Mounting Type：Through Hole
- Package / Case：TO-226-3, TO-92-3 (TO-226AA)
- Supplier Device Package：TO-92
- Grade：-
- Qualification：-
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Overview
The PN4119 is an N-channel JFET amplifier in a TO-92 package. It features ultra-high input impedance with gate reverse current of -10 pA at 25°C and -25 nA at 150°C. The saturation drain current (IDSS) ranges from 0.20 mA to 0.80 mA at VDS=10V, VGS=0. Gate-source breakdown voltage is -40V. Common-source forward transconductance (gfs) spans 100 µS to 700 µS. Input capacitance is 3 pF, and reverse transfer capacitance is 1.5 pF.
Feature Summary
- Ultra-high input impedance for minimal circuit loading
- Low power consumption with low IDSS
- Symmetrical geometry allowing interchangeable source and drain leads
Applications
- High-impedance amplifier circuits
- Low-power analog signal processing
- Precision sensor interfaces
Procurement Notes
Verify the specific suffix matches the required pinout and packaging configuration. Confirm RoHS compliance status for your region. Check datasheet revision date against manufacturing lot dates. Ensure storage temperature limits are respected during handling. Validate that the TO-92 lead form factor fits your PCB footprint requirements.
Selection Notes
Select based on required IDSS range and transconductance gain. Consider thermal derating above 25°C for total device dissipation. Evaluate capacitance values for high-frequency applications. Compare gate leakage specifications against ambient operating temperatures. Verify symmetry benefits for circuit layout flexibility.
Part Context
Linear Integrated Systems produces this discrete semiconductor using proprietary processes derived from Amelco and Intersil expertise. The component belongs to a family including 2N and SST series variants with different packages like SOT-23 and TO-72. The company focuses on high-performance analog devices founded in 1987.
Replacement Considerations
- PN4118
- PN4117
FAQ
Can the source and drain leads be interchanged?
Yes, due to symmetrical geometry, the units may be operated with source and drain leads interchanged.
What is the maximum gate-source voltage?
The absolute maximum rating for Gate-Source or Gate-Drain Voltage is -40V.
How is IDSS measured?
IDSS is measured during a 2 ms interval, 100 ms after power is applied, which is not a JEDEC condition.
