PTN3460BS/F3Y

Overview

The PTN3460BS/F3Y is an embedded DisplayPort to LVDS bridge IC manufactured by NXP Semiconductors. It converts DP streams from sources like CPUs or GPUs into LVDS format for display panels. The device supports link rates of 1.62 Gbit/s and 2.7 Gbit/s with 1-lane or 2-lane operation. It handles pixel clock frequencies up to 112 MHz, supporting single or dual bus LVDS signaling with 18-bit or 24-bit color depths. Power supply options include a single 3.3 V rail or dual 3.3 V/1.8 V rails. The component operates within a temperature range of 0 °C to 70 °C and is housed in a 56-terminal HVQFN package measuring 7 mm x 7 mm.

Feature Summary

• Embedded microcontroller and on-chip Non-Volatile Memory (NVM) enable flexible firmware updates.
• Supports EDID ROM emulation for panels lacking EDID ROM, accommodating up to seven different data structures.
• Provides programmable LVDS signal swing and center spreading to minimize EMI and compensate for channel attenuation.
• Features integrated panel power-up/down sequencing control and backlight PWM generation.

Applications

• All-in-One (AIO) platforms
• Notebook platforms
• Netbooks and net tops

Procurement Notes

Verify the specific firmware version associated with the F3Y suffix against official documentation before procurement. Firmware versions are not necessarily backwards compatible, and box labels indicate the specific version. Confirm that the required operating temperature range aligns with the commercial specification of 0 °C to 70 °C for this part variant.

Selection Notes

Select this component when interfacing eDP sources with LVDS displays requiring protocol conversion. Ensure the system design accommodates the HVQFN56 package dimensions and pitch. Verify compatibility with the required LVDS data packing formats (VESA or JEIDA) and color depth configurations. Consider the availability of I2C or AUX interfaces for configuration needs.

Part Context

The PTN3460BS/F3Y belongs to the PTN3460 series of bridge ICs designed for commercial and industrial applications. This series facilitates connectivity between embedded DisplayPort sources and LVDS panels. The 'F3Y' suffix denotes a specific firmware version within the PTN3460BS product line, distinguishing it from other firmware variants available in the same package.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided source material. Consult NXP Semiconductors for functional replacements or updated firmware versions if necessary.

FAQ

What is the function of the DEV_CFG pin?

The DEV_CFG pin sets the I2C-bus configuration mode. Pulling it low configures the device as an I2C slave with a low address, leaving it open sets a high address, and pulling it high enables master mode for reading external EEPROM.

How does the PTN3460 handle panels without EDID ROM?

The device emulates EDID ROM behavior, supporting EDID structure v1.3 and storing up to seven different EDID data structures on-chip, which avoids the need for specific changes in the system video BIOS.

What are the supported link rates for the DisplayPort receiver?

The PTN3460 supports Main Link rates of Reduced Bit Rate (1.62 Gbit/s) and High Bit Rate (2.7 Gbit/s), operating in either 1-lane or 2-lane modes.