SEARCH
— IC芯片 | 连接器 | 传感器 | 被动器件 —
The PX1011A-EL1,551 is a single-lane PCI Express electrical physical layer (PHY) compliant with Base Specification Rev. 1.0a and 1.1. It operates at 2.5 Gbit/s using an 8-bit parallel data interface running at 250 MHz with SSTL_2 signaling. The device integrates clock and data recovery (CDR), serializer/deserializer (SerDes), 8b/10b encoding, and elastic buffering. It supports power management states L0, L0s, and L1, dissipating less than 300 mW in normal mode. The component is housed in an LFBGA81 package and supports industrial temperature ranges.
Verify the specific ordering suffix to confirm lead-free status and temperature grade. The EL1 designation indicates the LFBGA81 package. Confirm RoHS compliance requirements against the /G suffix if lead-free solder is mandatory. Ensure the source document matches the exact part number variant required for the design.
Select this component when a dedicated single-lane PCIe PHY is needed for off-chip connectivity. Verify that the host MAC supports the enhanced PXPIPE interface with source synchronous clocks. Ensure voltage levels match the SSTL_2 class I signaling requirements and that the system can provide the necessary 100 MHz reference clock.
This component belongs to the PX1011A/PX1012A family of high-performance, low-power PCI Express PHYs originally manufactured by Philips Semiconductors. These devices are designed to handle low-level protocol and signaling tasks, providing superior performance to Media Access Control (MAC) layer devices in PCI Express architectures.
Public confirmed substitute part numbers: PX1012A-EL1/G.