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SC28L92A1BS,551 is listed in the UARTs (Universal Asynchronous Receiver Transmitter) range at ChipApex. The manufacturer field lists NXP USA Inc.. Its product description is IC UART DUAL W/FIFO 48HVQFN. Review the specifications below when checking this part for your BOM.
The SC28L92A1BS,551 is a Dual Universal Asynchronous Receiver/Transmitter (DUART) from NXP Semiconductors. It operates on a single 3.3 V or 5 V supply and supports data transfer rates up to 1 Mbit/s. The device features two independent full-duplex channels, each equipped with 16-byte FIFOs for both reception and transmission. It provides pin-programmable compatibility with Intel (80xxx) and Motorola (68xxx) bus interfaces. The component includes an on-chip crystal oscillator, programmable baud rate generators, and a watchdog timer for each receiver.
Verify the specific ordering suffix matches the HVQFN48 package variant. Confirm that the required bus interface mode aligns with the hardware configuration of the target microprocessor system. Ensure power supply voltage specifications are within the allowed 3.3 V or 5 V ranges for reliable operation.
Select this component when a pin-compatible replacement for SCC2692 or SC26C92 is needed with enhanced FIFO depth. Choose the HVQFN48 package for space-constrained designs requiring thermal enhancement. Verify that the required baud rates and bus timing constraints are supported by the internal clock selectors.
This part belongs to the SC28L92 family of DUARTs manufactured by NXP Semiconductors. It serves as a modernized successor to legacy UART controllers, offering deeper buffers and extended baud rate capabilities while maintaining backward compatibility with older bus standards.
SC28L92A1B
The bus interface is selected via the I/M pin. Connecting it HIGH configures the device for the Intel (80xxx) interface, while connecting it LOW configures it for the Motorola (68xxx) interface.
Yes, the FIFO fill capacity can be configured to operate at either 8 bytes or 16 bytes per channel. This is controlled by bit 3 of the MR0A register to ensure strict compliance with legacy devices if necessary.
The maximum data transfer rate is 1 Mbit/s, achievable with either a 1× or 16× clock derived from the programmable counter/timer or external clock inputs.
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