SI5010-B-GM

Overview

The Si5010-B-GM is a fully integrated clock and data recovery (CDR) IC designed for high-speed serial communication systems operating at OC-12/3 or STM-4/1 data rates. It utilizes DSPLL technology to eliminate external loop filter components, reducing noise entry points and ensuring optimal jitter performance. The device operates from a single 2.5 V supply over the industrial temperature range of –40°C to 85°C. Key electrical specifications include a typical power dissipation of 293 mW at OC-12, an RMS jitter generation of 1.6 mUI, and an output clock rate ranging from 150 MHz to 666 MHz. It features differential CML inputs and outputs with LVTTL control interfaces.

Feature Summary

• DSPLL technology eliminates external loop filter components for improved jitter performance
• Supports OC-12/3 and STM-4/1 data rates with multi-rate configuration via RATESEL pin
• Low power consumption: 293 mW typical at OC-12, 310 mW at OC-3
• Exceeds SONET/SDH jitter specifications per Bellcore GR-253-CORE and ITU-T G.958

Applications

• SONET/SDH routers
• Add/drop multiplexers
• Digital cross connects
• Board level serial links
• SONET/SDH test equipment
• Optical transceiver modules
• SONET/SDH regenerators

Procurement Notes

Verify the specific revision suffix 'B' in the part number Si5010-B-GM against current Silicon Laboratories documentation to ensure compatibility with design requirements. Confirm that the 20-lead QFN package dimensions and thermal pad layout match the recommended PCB layout provided in the datasheet. Ensure the system provides a stable 2.5 V supply and appropriate reference clock frequencies (19.44 MHz, 77.76 MHz, or 155.52 MHz) for proper PLL operation.

Selection Notes

Select the Si5010-B-GM for applications requiring low-jitter clock recovery at OC-12/3 or STM-4/1 speeds. The device supports two data rates configured by the RATESEL pin: 622.08 Mbps (OC-3/STM-1) and 155.52 Mbps (OC-12/STM-4). Ensure the application can accommodate the required 10 kΩ bias resistor on the REXT pin and provide AC-coupled differential inputs. The device requires a self-calibration sequence upon power-up for optimal performance.

Part Context

The Si5010 is part of the Si50x series of clock and data recovery devices from Silicon Laboratories. The '-GM' suffix indicates a 20-lead Quad Flat No-Lead (QFN) package with lead-free composition. The '-B' denotes the specific die revision. This component is distinct from programmable oscillators like the Si501/502/503 series found in other contexts, as it is a dedicated CDR solution rather than a frequency generator.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Designers should consult Silicon Laboratories for current alternative CDR solutions if the Si5010-B-GM is discontinued or unavailable.

FAQ

How is the internal self-calibration initiated?

Self-calibration is initiated by forcing a high-to-low transition on the PWRDN/CAL pin while a valid reference clock is supplied to the REFCLK input. The PWRDN/CAL pin must be held high for at least 1 µs before transitioning low.

What are the supported reference clock frequencies?

The Si5010 automatically configures for one of three reference clock frequencies: 19.44 MHz, 77.76 MHz, or 155.52 MHz, with a frequency accuracy tolerance of ±100 ppm.

What is the function of the LOL pin?

The Loss-of-Lock (LOL) pin is driven high when the recovered clock frequency deviates from the reference clock by more than the specified threshold (e.g., 450–750 ppm), indicating the PLL is out of lock.