SI5018-B-GMR

Overview

The Si5018-B-GMR is a fully integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-48/STM-16 rates, supporting up to 2.7 Gbps with forward error correction (FEC). The device utilizes DSPLL™ technology to eliminate external loop filter components, ensuring optimal jitter performance. It operates from a single 2.5 V supply over the industrial temperature range of –40 to 85 °C.

Feature Summary

• DSPLL™ technology eliminates external loop filter components
• Supports OC-48/STM-16 and FEC applications up to 2.7 GHz
• Low power consumption of 270 mW typical at OC-48
• 3.3 V tolerant control inputs

Applications

• SONET/SDH routers
• Add/drop multiplexers
• Digital cross connects
• SONET/SDH test equipment
• Optical transceiver modules

Procurement Notes

Verify that the ordering suffix 'R' corresponds to the tape and reel packaging option containing 2500 units per reel. Confirm the package type is the 20-lead Quad Flat No-Lead (QFN) with a 4x4 mm footprint. Ensure the component meets RoHS compliance standards as specified in the ordering guide.

Selection Notes

Select this component for SONET/SDH applications requiring OC-48/STM-16 data rates. Ensure the design accommodates a single 2.5 V supply voltage. Verify that the application supports the required reference clock frequencies between 19.44 MHz and 168.75 MHz. Consider the thermal resistance of 38 °C/W for heat dissipation planning.

Part Context

The Si5018 is part of the SiPHY family of CDR ICs. The '-B-' designation indicates the specific product revision. The '-GM' suffix denotes the 20-lead QFN package, while the additional 'R' specifies the tape and reel shipping configuration. This variant is manufactured by Silicon Laboratories Inc.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.

FAQ

How is PLL self-calibration initiated?

Self-calibration is initiated by forcing a high-to-low transition on the PWRDN/CAL pin while a valid reference clock is supplied. The pin must be held high for at least 1 μs before transitioning low.

What is the function of the REXT pin?

The REXT pin is used to connect an external 10 kΩ (1%) resistor to GND. This resistor sets the internal bias currents, which reduces power consumption compared to implementations using internal resistors.

How does the Loss-of-Lock (LOL) indicator work?

The LOL output is driven high when the recovered clock frequency deviates from the reference clock by more than the specified threshold (e.g., 450–750 ppm). It indicates that the PLL has lost frequency lock with the incoming data stream.