SI53106-A01AGMR

Overview

The SI53106-A01AGMR is a six-output, differential clock buffer and zero-delay buffer manufactured by Skyworks Solutions Inc. It meets Intel DB1200ZL specifications for PCIe Gen 1/2/3/4, SAS, SATA, Intel QPI, and Intel SMI applications. The device operates at 100 MHz or 133 MHz with a 3.3 V core supply (3.135–3.465 V) and a 1.05–3.3 V I/O supply. Key electrical parameters include a typical operating current of 19 mA on the VDD rail and 15 mA on the VDDA rail at 133 MHz in PLL mode. Output-to-output skew is typically 20 ps, with a maximum of 50 ps.

Feature Summary

• Six 0.7 V low-power, push-pull, HCSL-compatible outputs compliant with PCIe Gen 3 SRNS and Intel QPI/SMI jitter requirements.
• Integrated PLL optimized for 100 MHz and 133 MHz operation with selectable high-bandwidth, bypass, or low-bandwidth modes via hardware pin or SMBus.
• Individual hardware output enable (OE) pins for each of the six outputs to manage power consumption and signal integrity.
• Configurable SMBus address via SA_0 and SA_1 tri-level pins, supporting up to nine unique addresses on a single control network.

Applications

• Server systems requiring distributed reference clocks.
• Storage subsystems utilizing SAS and SATA interfaces.
• Datacenter infrastructure equipment.
• Enterprise switches and routers.

Procurement Notes

Verify the specific ordering suffix 'A01AGMR' against the manufacturer's current production status, as component availability may vary. Confirm that the 40-pin QFN package dimensions align with the target PCB land pattern design. Ensure the input clock source supports the required differential signaling levels and slew rates specified in the datasheet for optimal performance.

Selection Notes

Select this component when distributing reference clocks for Intel QPI, PCIe Gen 3/4, or Intel SMI where low phase jitter is critical. Choose the PLL mode for superior jitter cleaning or bypass mode if additive jitter constraints are minimal. Verify that the system requires exactly six differential outputs and that the 100 MHz or 133 MHz frequency options meet the design specifications.

Part Context

The SI53106 belongs to Skyworks' family of PCI Express and QPI clock buffers. It is designed to replace discrete buffering solutions by integrating the PLL, termination, and drive capabilities into a single 40-pin QFN package. This integration reduces board space and simplifies layout compared to using multiple standard logic buffers.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Consult Skyworks Solutions directly for alternative devices with higher output counts or different package configurations.