SI5315A-C-GM

Overview

The Si5315A-C-GM is a jitter-attenuating clock multiplier utilizing Skyworks DSPLL technology. It accepts dual differential clock inputs from 8 kHz to 644.53 MHz and generates two equal frequency-multiplied outputs within the same range. The device supports SyncE EEC options 1 and 2, providing ultra-low jitter generation of 0.23 ps RMS (1.875–20 MHz) and 0.47 ps RMS (12 kHz–20 MHz). It operates on a single supply voltage of 1.8 V, 2.5 V, or 3.3 V with a typical current draw of 25 mA at 2.5 V for LVPECL outputs. The component features programmable output formats including LVPECL, LVDS, CML, and CMOS, housed in a 6 x 6 mm 36-pin QFN package.

Feature Summary

• Dual PLL architecture supporting hitless switching between two input clocks
• Ultra-low phase noise: 0.23 ps RMS (1.875–20 MHz) and 0.47 ps RMS (12 kHz–20 MHz)
• Supports ITU-T G.8262 SyncE EEC options 1 and 2 with wander filtering
• Programmable loop bandwidth ranging from 60 Hz to 8.4 kHz

Applications

• Synchronous Ethernet line cards
• SONET OC-3/12/48 line cards
• PON OLT/ONU systems
• Carrier Ethernet switches and routers
• T1/E1/DS3/E3 line cards

Procurement Notes

Verify the specific speed grade suffix (A vs B) when ordering, as performance parameters such as maximum output frequency and supply current differ between grades. Confirm the operating voltage requirements align with the selected speed grade specifications. Ensure proper handling procedures are followed due to moisture sensitivity classification.

Selection Notes

Select the Si5315A variant for applications requiring output frequencies up to 644.53 MHz. Choose the Si5315B variant if the application requires a maximum output frequency of 125 MHz but offers lower power consumption. Verify that the external crystal or reference clock matches the required input frequency range of 8 kHz to 644.53 MHz.

Part Context

This component belongs to the Si531x family of synchronous Ethernet and telecom jitter attenuating clock multipliers. It is designed to replace traditional solutions requiring external VCXOs and discrete loop filter components by integrating the DSPLL technology on-chip. The device simplifies system design by providing pin-controlled configuration for frequency plans and clock selection.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.

FAQ

What is the maximum output frequency for the Si5315A speed grade?

The maximum output frequency for the Si5315A speed grade is 644.53 MHz.

Does the Si5315 require external components for the PLL loop filter?

No, the integrated DSPLL technology eliminates the need for external VCXO and loop filter components.

How does the device handle loss of the input reference clock?

The Si5315 provides holdover capability to continue generating a stable output clock and triggers Loss of Signal (LOS) and Loss of Lock (LOL) alarms.