SI5319B-C-GM

Overview

The SI5319B-C-GM is a jitter-attenuating precision M/N clock multiplier utilizing Skyworks' third-generation DSPLL technology. It accepts an input frequency from 2 kHz to 710 MHz and generates an output ranging from 2 kHz to 945 MHz, with select frequencies up to 1.4 GHz. The device features ultra-low jitter generation as low as 0.3 ps rms (50 kHz–80 MHz) and meets OC-192 GR-253-CORE specifications. It operates on a single supply of 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10% within an ambient temperature range of -40 °C to +85 °C.

Feature Summary

• Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input of 2 kHz to 710 MHz
• Ultra-low jitter generation as low as 0.3 ps rms (50 kHz–80 MHz)
• Integrated loop filter with digitally programmable bandwidth from 60 Hz to 8.4 kHz
• Supports LVPECL, LVDS, CML, and CMOS output signal formats

Applications

• 10G/40G/100G OTN line cards
• SONET/SDH OC-48/STM-16 and OC-192/STM-64 line cards
• GbE/10GbE, 1/2/4/8/10GFC line cards
• ITU G.709 and custom FEC line cards
• Synchronous Ethernet

Procurement Notes

Verify the specific speed grade associated with the 'B' suffix in the ordering guide to ensure the component meets the required maximum output frequency for the application. Confirm that the package type matches the design footprint requirements. Check for RoHS compliance status if environmental regulations apply to the manufacturing process.

Selection Notes

Select this component when sub 1 ps jitter performance is required for high-speed timing applications. Ensure the input clock source falls within the 2 kHz to 710 MHz range. Verify that the system power supply can provide the necessary current, which varies based on the selected output format and frequency. Use the DSPLLsim utility to optimize PLL divider settings and loop bandwidth.

Part Context

This part belongs to the Si5319 family of any-frequency precision clock multipliers. It is designed to eliminate the need for external VCXO and loop filter components by integrating these functions into a highly integrated PLL solution. The device supports I2C or SPI programming for flexible configuration of frequency translation ratios.

Replacement Considerations

Direct replacements within the same series include other speed grades such as SI5319A or SI5319C, provided the electrical specifications meet the design requirements. Verify pin compatibility and software register configurations when substituting between different speed grades.