SI5319B-C-GMR

Overview

The SI5319B-C-GMR is a jitter-attenuating precision M/N clock multiplier from Skyworks Solutions, utilizing third-generation DSPLL technology. It accepts an input frequency of 2 kHz to 710 MHz and generates an output ranging from 2 kHz to 945 MHz, with select frequencies up to 1.4 GHz. The device features ultra-low jitter generation as low as 0.3 ps rms (50 kHz–80 MHz) and meets OC-192 GR-253-CORE specifications. It operates on a single supply voltage of 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%. Key electrical parameters include a maximum output frequency of 945 MHz (select frequencies to 1.4 GHz), a maximum input frequency of 710 MHz, and a typical supply current of 217 mA at LVPECL format. The component is housed in a 6 x 6 mm 36-lead QFN package.

Feature Summary

• Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input of 2 kHz to 710 MHz.
• Ultra-low jitter generation as low as 0.3 ps rms (50 kHz–80 MHz) with selectable loop bandwidth from 60 Hz to 8.4 kHz.
• Supports ITU G.709 and custom OTN FEC ratios, including 255/238, 255/237, and 255/236.
• Programmable via I2C or SPI interface with integrated loop filter eliminating external VCXO requirements.

Applications

• 10G/40G/100G OTN line cards
• SONET/SDH OC-48/STM-16 and OC-192/STM-64 line cards
• GbE/10GbE, 1/2/4/8/10GFC line cards
• ITU G.709 and custom FEC line cards
• Synchronous Ethernet

Procurement Notes

Verify the specific 'B' speed grade suffix against the official Skyworks ordering guide to confirm the maximum output frequency capabilities relative to other variants in the SI5319 family. Ensure the 'GMR' suffix corresponds to the correct tape-and-reel packaging configuration required for surface-mount assembly processes. Confirm RoHS compliance status through the manufacturer's latest documentation.

Selection Notes

Select this component for applications requiring sub-1 ps jitter performance and any-frequency synthesis without external loop filter components. The device supports multiple output formats including LVPECL, LVDS, CML, and CMOS. Consider the digital programmability of the PLL loop bandwidth for optimizing jitter attenuation at specific application levels. Ensure the input clock source is compatible with the 2 kHz to 710 MHz range.

Part Context

The SI5319 belongs to Skyworks' DSPLL family of timing solutions. This series integrates the loop filter and eliminates the need for external VCXOs, providing a highly compact solution for high-performance timing applications. The device is designed to replace discrete PLL circuits while offering superior jitter attenuation and frequency translation capabilities across a wide operating range.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Verify compatibility with existing board layouts due to the 36-QFN package dimensions. Check if alternative speed grades within the SI5319 family meet the specific frequency requirements of the design.