SI5319C-C-GMR

Overview

The Si5319C-C-GMR is a jitter-attenuating precision M/N clock multiplier utilizing Skyworks' third-generation DSPLL technology. It accepts an input frequency from 2 kHz to 710 MHz and generates an output from 2 kHz to 945 MHz, with select frequencies up to 1.4 GHz. The device features ultra-low jitter generation as low as 0.3 ps rms (50 kHz–80 MHz) and includes an integrated loop filter with digitally selectable bandwidths ranging from 60 Hz to 8.4 kHz. It operates on a single supply voltage of 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10% and provides one configurable differential or single-ended output in LVPECL, LVDS, CML, or CMOS formats.

Feature Summary

• Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input of 2 kHz to 710 MHz
• Ultra-low jitter generation as low as 0.3 ps rms (50 kHz–80 MHz)
• Integrated loop filter with selectable digital loop bandwidth from 60 Hz to 8.4 kHz
• Supports I2C or SPI programmability with on-chip voltage regulator for 1.8 V, 2.5 V, or 3.3 V operation

Applications

• 10G/40G/100G OTN line cards
• SONET/SDH OC-48/STM-16 and OC-192/STM-64 line cards
• GbE/10GbE, 1/2/4/8/10GFC line cards
• ITU G.709 and custom FEC line cards
• Synchronous Ethernet

Procurement Notes

Verify the specific ordering suffix against the manufacturer's current datasheet to confirm package type and tape/reel specifications. Ensure the design supports the required supply voltage range (1.71 V to 3.63 V) and operating temperature range (-40 °C to +85 °C). Confirm interface compatibility for I2C or SPI control modes during system integration.

Selection Notes

Select this component when sub-1 ps jitter performance is required for high-speed serial applications. The device eliminates external VCXO and loop filter components due to its integrated DSPLL architecture. Use the DSPLLsim utility to determine optimal PLL divider settings and loop bandwidth configurations for specific input/output frequency combinations to minimize phase noise and power consumption.

Part Context

The Si5319 belongs to the DSPLL family of any-frequency precision clock multipliers. It is designed to replace discrete PLL solutions by integrating the loop filter and reference oscillator circuitry. The device supports various frequency translations for Synchronous Ethernet and meets OC-192 GR-253-CORE jitter specifications.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.