SI5324B-C-GM

Overview

The Skyworks SI5324B-C-GM is a low-bandwidth, jitter-attenuating precision clock multiplier utilizing third-generation DSPLL technology. It accepts two input clocks from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz, with select frequencies reaching 1.4 GHz. The device features digitally programmable loop bandwidths between 4 Hz and 525 Hz, achieving ultra-low jitter outputs as low as 290 fs rms (12 kHz–20 MHz). It supports configurable signal formats including LVPECL, LVDS, CML, and CMOS, operates on a single supply of 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, and is housed in a 6 x 6 mm 36-lead QFN package.

Feature Summary

• Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from inputs up to 710 MHz
• Ultra-low jitter performance: 290 fs rms (12 kHz–20 MHz) and 320 fs rms (50 kHz–80 MHz)
• Digitally programmable loop bandwidth (4–525 Hz) with integrated loop filter eliminating external components
• Hitless input clock switching with phase build-out and digital hold capability

Applications

• Broadcast video (3G/HD/SD-SDI, Genlock)
• Packet Optical Transport Systems (P-OTS), MSPP
• SONET OC-48/192/768, SDH/STM-16/64/256 line cards
• GbE/10/40/100G Synchronous Ethernet (LAN/WAN)

Procurement Notes

Verify the specific speed grade suffix 'B' against the manufacturer's ordering guide to confirm frequency limits and electrical characteristics. Confirm RoHS compliance and Pb-free status requirements for the target assembly process. Ensure the 36-lead QFN land pattern matches the official PCB layout specifications provided in the datasheet.

Selection Notes

Select this component when sub-1 ps jitter performance is required with loop bandwidths between 4 Hz and 525 Hz. Verify that the application requires two independent output clocks derived from a common source. Check if the system supports I2C or SPI programming for frequency synthesis configuration and if hitless switching between synchronous inputs is necessary.

Part Context

The SI5324B-C-GM belongs to the Si5324 family of any-frequency precision clock multipliers. The 'B' suffix denotes a specific speed grade within the series, distinguishing it from other variants like Si5324A, Si5324C, or Si5324D which may have different frequency or timing specifications. All variants share the same core DSPLL architecture and QFN-36 package.

Replacement Considerations

Direct replacements include other Si5324 speed grades (Si5324A-C-GM, Si5324C-C-GM, Si5324D-C-GM) if their specific frequency limits meet the design requirements. Cross-family replacement with Si5327 or Si5345 devices requires verification of pin compatibility and feature sets.