SI5324E-C-GM

Overview

The Si5324E-C-GM is a low-bandwidth, jitter-attenuating precision clock multiplier utilizing Skyworks Solutions' 3rd-generation DSPLL technology. It accepts two input clocks from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz, with select frequencies up to 1.4 GHz. The device features digitally programmable loop bandwidths between 4 Hz and 525 Hz, achieving ultra-low jitter outputs as low as 290 fs rms (12 kHz–20 MHz) and 320 fs rms (50 kHz–80 MHz). It supports configurable signal formats including LVPECL, LVDS, CML, and CMOS, operates on a single supply of 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, and is housed in a 6 x 6 mm 36-lead QFN package.

Feature Summary

• Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input range of 2 kHz to 710 MHz
• Ultra-low jitter performance: 290 fs rms (12 kHz–20 MHz) and 320 fs rms (50 kHz–80 MHz)
• Digitally programmable integrated loop filter with selectable bandwidth from 4 Hz to 525 Hz
• Configurable output signal formats per channel: LVPECL, LVDS, CML, or CMOS

Applications

• Broadcast video systems including 3G/HD/SD-SDI and Genlock
• Packet Optical Transport Systems (P-OTS) and MSPP
• SONET OC-48/192/768 and SDH/STM-16/64/256 line cards
• 1/2/4/8/10G Fibre Channel line cards
• GbE/10/40/100G Synchronous Ethernet (LAN/WAN)

Procurement Notes

Verify the specific speed grade suffix 'E' against the manufacturer's ordering guide to confirm maximum output frequency limits and lock/settle time characteristics relative to other grades. Ensure the operating environment remains within the specified ambient temperature range of –40 °C to +85 °C and that the selected supply voltage matches the required output format specifications.

Selection Notes

Select this component for applications requiring sub 1 ps jitter performance with narrow loop bandwidths. The Si5324E-C-GM requires careful consideration of lock and settle times, which are longer than lower-grade variants due to its optimized jitter attenuation capabilities. Use the DSPLL sim utility to determine optimal PLL divider settings and loop bandwidth configurations to minimize phase noise and power consumption for the specific frequency plan.

Part Context

The Si5324 series comprises any-frequency jitter attenuating clock multipliers based on DSPLL technology. This family eliminates the need for external VCXO and filter components by integrating these functions on-chip. The Si5324E-C-GM represents a specific speed grade within the Si5324 lineup, distinguished by its performance metrics regarding lock time and maximum output frequency capabilities compared to other available grades.

Replacement Considerations

Direct replacements within the same package and pinout include other speed grades of the Si5324 series, such as the Si5324A-C-GM, Si5324B-C-GM, Si5324C-C-GM, and Si5324D-C-GM. Note that substituting with a different grade may alter lock time, settle time, and maximum output frequency specifications.