SI53328-B-GMR

Clock Buffers, Drivers Overview

The Skyworks SI53328-B-GMR is a low-jitter LVPECL fanout clock buffer featuring a 2:1 selectable input multiplexer and two banks of three LVPECL outputs. It accepts single-ended LVCMOS inputs and operates over a frequency range from DC to 200 MHz. The device includes built-in LDOs for high power supply noise rejection (PSRR) and independent output enables per bank. Packaged in a 24-QFN (4x4 mm) form factor, it supports supply voltages of 2.5 V or 3.3 V with a typical core current of 80 mA.

Clock Buffers, Drivers Feature Summary

• 2:1 Input Mux with Single-Ended LVCMOS Input
• Two Independent Banks of 3 LVPECL Outputs
• Built-in LDOs for High PSRR Performance
• Frequency Range: DC to 200 MHz

Clock Buffers, Drivers Applications

• Clock distribution in noisy environments
• Redundant clocking systems
• Low-jitter clock tree generation

Clock Buffers, Drivers Procurement Notes

Verify the specific ordering suffix against the manufacturer's official documentation to confirm package type and temperature range. Confirm that the GMR suffix corresponds to the required reel packaging format for automated assembly processes.

Clock Buffers, Drivers Selection Notes

Select this component when single-ended LVCMOS inputs must be converted to multiple LVPECL outputs within a 200 MHz limit. The dual-bank architecture allows for independent control of output groups via separate enable pins, suitable for applications requiring segmented clock gating.

Clock Buffers, Drivers Part Context

This part belongs to the Si53320–28 family of universal LVPECL fanout buffers. Unlike other family members that support differential inputs, the Si53328 is specifically configured for single-ended LVCMOS inputs while maintaining the family's low-jitter characteristics and internal power regulation features.

Clock Buffers, Drivers Replacement Considerations

Direct functional substitutes within the same family include the Si53327-B-GM, which offers identical specifications but accepts any-format (differential) inputs instead of single-ended LVCMOS.