SI5335C-B11043-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The Skyworks SI5335C-B11043-GM is a web-customizable, any-frequency, any-output quad clock generator and buffer. It synthesizes four non-integer-related frequencies up to 350 MHz using MultiSynth technology, ensuring 0 ppm frequency synthesis error. The device supports three independent, pin-selectable configurations and features flexible output drivers capable of LVPECL, LVDS, CML, HCSL, CMOS, SSTL, or HSTL formats with independent voltage levels (1.5, 1.8, 2.5, or 3.3 V). It operates on a single core supply of 1.8, 2.5, or 3.3 V, includes loss-of-signal alarm functionality, and is housed in a 4 x 4 mm, 24-QFN package.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Four independent output banks supporting differential pairs or single-ended outputs with configurable formats including LVPECL, LVDS, CML, HCSL, CMOS, SSTL, and HSTL.
• MultiSynth fractional divider technology guarantees 0 ppm frequency synthesis error for all outputs.
• Supports up to three independent, user-assignable, pin-selectable device configurations within a single IC.
• Two selectable PLL loop bandwidths (1.6 MHz or 475 kHz) for jitter attenuation in applications like PCIe and DSL.

Clock Generators, PLLs, Frequency Synthesizers Applications

• PCI Express Gen 1/2/3/4 common clock and SRNS compliant systems
• Ethernet switch/router and 1 GbE/10 GbE interfaces
• Processor and FPGA clocking
• DSL jitter attenuation

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory configuration encoded in the ordering suffix B11043 against the system requirements, as this part is web-customized. Confirm that the required pin-selectable control functions (SSENB, RESET, OEB, FS1, FS0) are correctly assigned during the ClockBuilder Pro design phase. Ensure the selected core supply voltage (1.8 V, 2.5 V, or 3.3 V) matches the board's power delivery network specifications.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when multiple distinct clock frequencies are required from a single source with zero ppm error. Choose between the 1.6 MHz or 475 kHz loop bandwidth based on whether jitter attenuation or faster lock time is prioritized. Ensure the output driver voltage levels match the receiving devices' input requirements, as each bank can be configured independently. Verify that the input reference source (crystal, CMOS, or differential) is compatible with the configured input pins.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the Si5335 family of highly flexible clock generators manufactured by Skyworks Solutions. The 'C' in the model number typically denotes a specific performance grade or revision within the series, while the alphanumeric suffix defines the unique frequency plan and pin configuration. It replaces multiple discrete clock oscillators and buffers in complex digital systems.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Direct pin-to-pin replacements may exist within the Si5335A or Si5335B families if the frequency plan and output drive strengths are identical. However, due to the custom nature of the B11043 configuration, a generic Si5335 device must be reconfigured via ClockBuilder Pro to function as a substitute. Verify that the replacement part supports the same output formats and voltage levels.