SI5335D-B04749-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5335D-B04749-GMR is a web-customizable, any-frequency, any-output quad clock generator and buffer manufactured by Skyworks Solutions. It synthesizes four non-integer-related frequencies up to 350 MHz using MultiSynth fractional divider technology, ensuring 0 ppm frequency synthesis error. The device supports three independent pin-selectable configurations and features flexible input references including external crystals (25/27 MHz), CMOS, SSTL/HSTL, and differential inputs. Outputs are configurable as LVPECL, LVDS, CML, HCSL, CMOS, or SSTL/HSTL with independent voltage levels of 1.5, 1.8, 2.5, or 3.3 V. It operates on a single core supply of 1.8, 2.5, or 3.3 V within an ambient temperature range of –40 to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• MultiSynth Technology: Synthesizes four completely non-integer-related frequencies up to 350 MHz with 0 ppm frequency synthesis error.
• Flexible Input Support: Accepts external crystals (25/27 MHz), CMOS (10–200 MHz), SSTL/HSTL (10–350 MHz), and differential inputs (10–350 MHz).
• Configurable Outputs: Supports up to four differential pairs or eight single-ended outputs in formats including LVPECL, LVDS, CML, HCSL, CMOS, and SSTL/HSTL.
• Pin-Selectable Configurations: Enables one device to replace three separate clock generators via three independent user-assignable configurations.

Clock Generators, PLLs, Frequency Synthesizers Applications

• PCI Express Gen 1/2/3/4 common clock generation and jitter attenuation
• Ethernet switch/router and 1 GbE/10 GbE timing
• DSL jitter attenuation and MSAN/DSLAM/PON systems
• Processor and FPGA clocking
• Broadcast video/audio timing

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory configuration programmed into the SI5335D-B04749-GMR against system requirements. As this is a web-customized component, standard electrical parameters apply, but output frequencies, formats, and control pin assignments are unique to the ordering suffix. Confirm compatibility with the ClockBuilder Pro utility for any necessary design adjustments.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when multiple distinct clock frequencies are required from a single source with zero ppm error. Ensure the input reference matches available system clocks (crystal, CMOS, or differential). Verify that the required output voltage levels (1.5V, 1.8V, 2.5V, or 3.3V) align with the target receivers. Consider the 4x4 mm 24-QFN package constraints and thermal dissipation for the intended operating environment.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The SI5335D-B04749-GMR belongs to the Si5335 family of highly flexible clock generators. The 'D' suffix typically denotes specific performance or feature variations within the family, while the long numeric code indicates a unique factory-programmed configuration. This part replaces multiple discrete oscillators and buffers, simplifying PCB layout and reducing bill-of-materials count in complex digital systems.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Direct replacements must be other Si5335 variants with identical factory configurations. Generic Si5335 parts will not function correctly without reprogramming. Verify that substitute parts support the same input/output frequency ranges and voltage levels specified in the original design.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum output frequency supported by the SI5335D?

The device supports output frequencies up to 350 MHz for LVPECL, LVDS, CML, SSTL, and HSTL formats. HCSL outputs are supported up to 250 MHz, and CMOS outputs up to 200 MHz.

How does the device handle frequency synthesis error?

Using Skyworks' patented MultiSynth fractional divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis error regardless of the configuration.

Can the device operate in both clock generator and buffer modes?

Yes, the Si5335 can be configured as either a clock generator (using the PLL) or a clock buffer (PLL bypass mode). Loop bandwidth settings of 1.6 MHz or 475 kHz are available for jitter attenuation in generator mode.