SI5335D-B04782-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5335D-B04782-GMR is a web-customizable, any-frequency, any-output quad clock generator and buffer manufactured by Skyworks Solutions. It synthesizes four non-integer-related frequencies up to 350 MHz using MultiSynth fractional divider technology, ensuring 0 ppm frequency synthesis error. The device supports independent output configurations including LVPECL, LVDS, CML, HCSL, CMOS, SSTL, and HSTL formats with selectable supply voltages of 1.5, 1.8, 2.5, or 3.3 V. It operates on a single core supply (1.8, 2.5, or 3.3 V) and features two selectable PLL loop bandwidths (1.6 MHz or 475 kHz) for jitter attenuation. The component is housed in a 4 x 4 mm, 24-lead QFN package.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Four independent outputs supporting any frequency up to 350 MHz with 0 ppm synthesis error
• Configurable as clock generator or buffer with low phase jitter (0.7 ps RMS typical)
• Supports multiple input references: external crystal (25/27 MHz), CMOS, differential, SSTL/HSTL
• Up to five user-assignable pin functions for spread spectrum control, reset, and frequency plan selection

Clock Generators, PLLs, Frequency Synthesizers Applications

• PCI Express Gen 1/2/3/4 common clock and SRNS compliant systems
• Ethernet switch/router and 1 GbE/10 GbE interfaces
• DSL jitter attenuation and telecom line cards
• Processor and FPGA clocking
• Broadcast video/audio timing

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory configuration encoded in the B04782 suffix against system requirements. Confirm that the required input reference type (crystal vs. CMOS/differential) matches the design. Ensure the target output voltage levels (1.5V, 1.8V, 2.5V, or 3.3V) are supported by the chosen VDDO supplies. Validate that the operating temperature range (-40 to +85 °C) meets environmental specifications.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model if the application requires four distinct, non-integer-related clock frequencies from a single device. Choose between the 1.6 MHz or 475 kHz loop bandwidth based on whether jitter attenuation or fast lock time is prioritized. Ensure the design accommodates the 24-QFN package thermal requirements. Verify compatibility with the ClockBuilder Pro utility for final configuration validation.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the Si5335 family of highly flexible clock generators. The 'D' suffix typically denotes a specific performance grade or feature set within the series, while the alphanumeric code defines the unique factory-programmed frequency plan and pin configuration. It replaces multiple discrete oscillators and buffers in complex digital systems.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Direct replacements must match the 24-QFN footprint and pinout. Substitute parts must support the same maximum output frequency (350 MHz) and compatible output driver formats. Verify that alternative devices offer similar jitter performance and configurable I/O voltage levels.