SI5335D-B04988-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5335D-B04988-GM is a web-customizable, any-frequency, any-output quad clock generator and buffer from Skyworks Solutions. It synthesizes four non-integer-related frequencies up to 350 MHz using MultiSynth fractional divider technology, ensuring 0 ppm frequency synthesis error. The device supports flexible input references including external crystals (25/27 MHz), CMOS, SSTL/HSTL, and differential inputs. Outputs are independently configurable for LVPECL, LVDS, CML, HCSL, CMOS, or SSTL/HSTL formats with selectable voltage levels of 1.5, 1.8, 2.5, or 3.3 V. It features low phase jitter of 0.7 ps RMS, two selectable PLL loop bandwidths (1.6 MHz or 475 kHz), and loss-of-signal alarm functionality.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Four independent output banks supporting any frequency up to 350 MHz with 0 ppm synthesis error
• Configurable as clock generator or buffer with three pin-selectable device configurations
• Low phase jitter of 0.7 ps RMS and selectable PLL loop bandwidths (1.6 MHz or 475 kHz)
• Flexible input options: 25/27 MHz crystal, CMOS, SSTL/HSTL, or differential signals

Clock Generators, PLLs, Frequency Synthesizers Applications

• PCI Express Gen 1/2/3/4 common clock and SRNS compliant systems
• Ethernet switch/router and 1 GbE/10 GbE interfaces
• DSL jitter attenuation and telecom line cards
• Processor and FPGA clocking in broadcast video/audio timing

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory configuration encoded in the B04988 suffix via the official Skyworks ClockBuilder Pro tool or datasheet ordering section. Confirm package type is 24-QFN and operating temperature range is –40 to +85 °C. Check current distributor availability as custom parts may have restricted supply status.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this part when multiple distinct clock frequencies are required from a single source with zero ppm error. Ensure the input reference matches available system clocks (crystal vs. driven input). Verify that the required output voltage levels (1.5V–3.3V) and formats (LVPECL, LVDS, etc.) are supported by the configured outputs. Consider loop bandwidth settings for jitter attenuation requirements in PCIe or DSL applications.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5335 family of highly flexible clock generators. The 'D' suffix typically denotes specific electrical or packaging variations within the series, while 'GMR' indicates tape-and-reel packaging. It replaces multiple discrete clock oscillators and buffers, simplifying PCB layout and reducing component count in high-speed digital designs.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Direct replacements require identical frequency plans and output configurations. Generic Si5335 variants may differ in loop bandwidth options or input/output capabilities. Verify compatibility with existing control pins (P1-P6) and power supply requirements before substitution.