SI5335D-B05170-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5335D-B05170-GM is a web-customizable, any-frequency, any-output quad clock generator and buffer from Skyworks Solutions. It synthesizes four non-integer-related frequencies up to 350 MHz using MultiSynth fractional divider technology, ensuring 0 ppm frequency synthesis error. The device supports flexible input references including external crystals (25/27 MHz), CMOS, SSTL/HSTL, and differential inputs. Outputs are independently configurable for LVPECL, LVDS, CML, HCSL, CMOS, or SSTL/HSTL formats with selectable supply voltages of 1.5, 1.8, 2.5, or 3.3 V. It operates on a single core supply (1.8, 2.5, or 3.3 V) within an ambient temperature range of –40 to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Four independent output banks supporting any frequency (< 350 MHz) with 0 ppm synthesis error via MultiSynth technology
• Configurable as clock generator or buffer with two selectable PLL loop bandwidths (1.6 MHz or 475 kHz)
• Supports three independent, pin-selectable device configurations and up to five user-assignable control pins
• Low phase jitter performance (0.7 ps RMS typical) and compliance with PCIe Gen 1/2/3/4 common clock standards

Clock Generators, PLLs, Frequency Synthesizers Applications

• PCI Express Gen 1/2/3/4 systems and jitter attenuation
• Ethernet switch/router and 1 GbE/10 GbE interfaces
• DSL jitter attenuation and telecom line cards
• Processor and FPGA clocking in broadcast video/audio timing

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory configuration encoded in the B05170 suffix against the system requirements using the ClockBuilder Pro utility. Confirm that the GMR tape-and-reel packaging matches the assembly line specifications. Ensure the selected PLL loop bandwidth and output driver formats align with the target application's jitter and signal integrity constraints.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when multiple distinct clock frequencies are required from a single source without integer relationships. Choose between the 1.6 MHz and 475 kHz loop bandwidth settings based on whether jitter attenuation or fast lock time is prioritized. Ensure the output voltage levels (1.5V–3.3V) match the receiving devices' input requirements for LVPECL, LVDS, or CMOS interfaces.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the Si5335 family of highly flexible clock generators. The 'D' variant typically denotes specific electrical characteristics or package options within the series, while the alphanumeric suffix defines the unique frequency plan and pin configuration programmed at the factory. It serves as a replacement for multiple discrete oscillators and buffers in complex digital systems.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Direct functional replacements within the same family include other Si5335 variants with different suffixes (e.g., SI5335A/B/D-xxxxxx-GM) that share the same 24-QFN package and pinout but offer different pre-programmed frequency plans. Verify compatibility by comparing the required output frequencies and formats.