SI5335D-B05223-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The Skyworks SI5335D-B05223-GMR is a web-customizable, any-frequency, any-output quad clock generator and buffer. It synthesizes four non-integer-related frequencies up to 350 MHz using MultiSynth fractional divider technology, ensuring 0 ppm frequency synthesis error. The device supports flexible input references including external crystals (25/27 MHz), CMOS, SSTL/HSTL, and differential inputs. Outputs are independently configurable for LVPECL, LVDS, CML, HCSL, CMOS, or SSTL/HSTL formats with selectable supply voltages of 1.5, 1.8, 2.5, or 3.3 V. It features low phase jitter of 0.7 ps RMS, two selectable PLL loop bandwidths (1.6 MHz or 475 kHz), and loss-of-signal alarm functionality.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Four independent output banks supporting any frequency up to 350 MHz with 0 ppm synthesis error
• Configurable as clock generator or buffer with three pin-selectable device configurations
• Low phase jitter of 0.7 ps RMS and selectable PLL loop bandwidths (1.6 MHz or 475 kHz)
• Flexible input options: 25/27 MHz crystal, CMOS, SSTL/HSTL, or differential signals

Clock Generators, PLLs, Frequency Synthesizers Applications

• PCI Express Gen 1/2/3/4 common clock and SRNS compliant systems
• Ethernet switch/router and 1 GbE/10 GbE interfaces
• Processor and FPGA clocking
• DSL jitter attenuation and telecom line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory configuration encoded in the B05223 suffix via the official datasheet ordering information section. Confirm that the -GMR suffix indicates tape-and-reel packaging suitable for automated assembly. Ensure compatibility with the required input reference type and output voltage levels defined in the custom design.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when multiple distinct clock frequencies are required from a single source with strict jitter constraints. Choose between the 1.6 MHz and 475 kHz loop bandwidth settings based on whether jitter attenuation or faster lock time is prioritized. Verify that the available user-assignable control pins meet system requirements for spread spectrum, reset, and frequency plan selection.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the Si5335 family of highly flexible clock generators. The 'D' variant typically denotes specific electrical or package characteristics within the series, while the alphanumeric suffix defines the unique factory-programmed frequency plan and pin configuration. It replaces multiple discrete oscillators and buffers in complex digital systems.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Direct replacements require identical frequency plans and pin configurations. Generic Si5335 devices cannot substitute this part without reconfiguration. Check for newer revisions in the Si5335 family that may offer updated packaging or performance metrics while maintaining functional compatibility.