SI5335D-B15708-GMR

Overview

The Skyworks SI5335D-B15708-GMR is a web-customizable, any-frequency, any-output quad clock generator and buffer. It synthesizes four non-integer-related frequencies up to 350 MHz using MultiSynth fractional divider technology, ensuring 0 ppm frequency synthesis error. The device supports flexible input references including external crystals (25/27 MHz), CMOS, SSTL/HSTL, and differential inputs. Outputs are independently configurable for LVPECL, LVDS, CML, HCSL, CMOS, or SSTL/HSTL formats with selectable supply voltages of 1.5, 1.8, 2.5, or 3.3 V. It features two selectable PLL loop bandwidths (1.6 MHz or 475 kHz) for jitter attenuation and operates on a single core supply of 1.8, 2.5, or 3.3 V within the -40 to +85 °C temperature range.

Feature Summary

• Four independent output banks supporting any frequency (< 350 MHz) with 0 ppm synthesis error via MultiSynth technology
• Configurable as clock generator or buffer with three pin-selectable device configurations
• Flexible input support: External crystal, CMOS (10-200 MHz), SSTL/HSTL, and Differential (10-350 MHz)
• Independent output voltage selection (1.5, 1.8, 2.5, 3.3 V) and format compatibility (LVPECL/LVDS/CML/HCSL/CMOS/SSTL/HSTL)

Applications

• PCI Express Gen 1/2/3/4 common clock and SRNS compliant systems
• Ethernet switch/router and 1 GbE/10 GbE interfaces
• DSL jitter attenuation and telecom line cards
• Processor and FPGA clocking in broadcast video/audio timing

Procurement Notes

Verify the specific factory configuration encoded in the ordering suffix B15708 against the target system requirements using the ClockBuilder Pro utility. Confirm that the GMR suffix indicates tape-and-reel packaging if automated assembly is required. Ensure the design accounts for the moisture sensitivity level indicated in the datasheet prior to reflow soldering.

Selection Notes

Select this component when multiple distinct clock frequencies are needed from a single source without integer relationships. Choose between the 1.6 MHz and 475 kHz loop bandwidth settings based on whether PCIe or DSL jitter attenuation is prioritized. Ensure the output driver voltage matches the load requirements, as each bank can be set independently to 1.5, 1.8, 2.5, or 3.3 V.

Part Context

This part belongs to the Si5335 family of highly flexible clock generators. The 'D' variant typically denotes specific performance or package characteristics within the series, while the alphanumeric suffix defines the custom frequency plan and control pin assignments programmed by Skyworks Solutions during manufacturing.

Replacement Considerations

Direct pin-to-pin replacements within the same family require identical frequency plans and control pin mappings. Verify that alternative SKUs match the specific output formats and voltage levels configured in the B15708 suffix. Cross-model substitution may require redesigning the control logic if pin functions differ.