SI5345B-B05791-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5345B-B05791-GMR is a low-jitter, 10-output jitter attenuator and clock multiplier from the Si5345 family. It utilizes fourth-generation DSPLL and MultiSynth technologies to generate any frequency combination up to 350 MHz from any input frequency. The device features four inputs (differential or LVCMOS) and ten configurable outputs supporting LVDS, LVPECL, LVCMOS, CML, and HCSL formats. Key electrical parameters include an ultra-low jitter of 90 fs rms, a differential input range of 8 kHz to 750 MHz, and an output range of 100 Hz to 350 MHz. It operates on a 1.8 V core voltage with independent 3.3 V, 2.5 V, or 1.8 V output supplies, housed in a 64-QFN package.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any combination of output frequencies from any input frequency using integer and fractional synthesis.
• Features ultra-low jitter performance of 90 fs rms for high-speed data applications.
• Supports hitless input clock switching between fractionally related inputs.
• Includes programmable jitter attenuation bandwidth ranging from 0.1 Hz to 4 kHz.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm factory preprogramming details. Confirm availability status as custom part numbers may have restricted supply channels. Ensure the serial interface configuration matches the system requirements before finalizing procurement.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when requiring up to ten outputs with frequencies up to 350 MHz and ultra-low jitter specifications. Verify that the input signal format (differential or LVCMOS) falls within the supported ranges of 8 kHz to 750 MHz. Ensure the application environment temperature remains within the -40 to +85 °C operating range specified for this device.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This device belongs to the Si5345 Rev D family, which integrates fourth-generation DSPLL technology. It serves as a versatile clock solution for telecommunications and networking infrastructure, offering flexible frequency generation and robust jitter attenuation capabilities compared to standard clock generators.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Direct replacements within the same family include other Si5345B variants with different factory preprogrammed configurations. Verify that the substitute part number supports the required 10-output count and 350 MHz maximum frequency limit.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum output frequency for the Si5345B variant?

The Si5345B variant supports output frequencies up to 350 MHz.

Does the device support locking to gapped input clocks?

Yes, the DSPLL supports locking to gapped input clocks, provided the minimum frequency is 10 MHz with no more than two missing cycles out of every eight.

How is the loop filter implemented in this device?

The loop filter is fully integrated on-chip, eliminating the need for external discrete components and reducing noise coupling risks.