SI5345B-B06755-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5345B-B06755-GMR is a 10-output jitter attenuator and clock multiplier from the Si5345 family, manufactured by Skyworks Solutions. It utilizes fourth-generation DSPLL and MultiSynth technologies to generate any combination of output frequencies from any input frequency. The device supports differential inputs up to 750 MHz and LVCMOS inputs up to 250 MHz. Output frequencies range from 100 Hz to 350 MHz for differential formats and 100 Hz to 250 MHz for LVCMOS. It features ultra-low jitter performance of 90 fs rms and meets ITU-T G.8262 SyncE requirements. The component operates within a temperature range of -40°C to +85°C and is housed in a 64-QFN package.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any combination of output frequencies from any input frequency using integer and fractional synthesis.
• Features ultra-low jitter performance of 90 fs rms with digitally programmable jitter attenuation bandwidth.
• Supports hitless input clock switching, free-run modes, and holdover capabilities for high reliability.
• Includes in-circuit programmable non-volatile memory (NVM) for persistent configuration storage.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory preprogrammed configuration associated with the B06755 suffix against the required system specifications. Confirm that the GMR tape-and-reel packaging aligns with automated assembly requirements. Ensure compatibility with the ClockBuilder Pro software version used for final validation. Check for RoHS compliance documentation if required by local regulations.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when ten independent output clocks are required with strict jitter constraints. The B-series designation indicates a maximum output frequency limit of 350 MHz, suitable for standard networking and telecom applications. Verify that the input source matches the supported differential or LVCMOS ranges. Consider the integrated loop filter benefits over discrete solutions for noise reduction.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5345 Rev D family, which integrates DSPLL and MultiSynth technologies. The Si5345 variant specifically provides four inputs and ten outputs in a 64-QFN package. It is designed for high-performance clock generation where jitter attenuation and frequency flexibility are critical. The family supports various output voltage standards including LVDS, LVPECL, and HCSL.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

The SI5345A-D-GMR offers higher output frequencies up to 1028 MHz but may require different layout considerations. The SI5345C-D-GMR supports integer-only synthesis, which simplifies configuration but reduces frequency flexibility. Ensure pinout and package dimensions remain compatible during substitution.