SI5345D-B00014-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The Skyworks SI5345D-B00014-GMR is a low-jitter, 10-output clock multiplier and jitter attenuator from the Si5345 family. It utilizes fourth-generation DSPLL and MultiSynth technologies to generate any frequency combination up to 350 MHz with ultra-low jitter of 90 fs rms. The device features four inputs (differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz) and ten configurable outputs supporting LVDS, LVPECL, LVCMOS, CML, and HCSL formats. It operates on a core voltage of 1.8 V ±5% and an I/O voltage of 3.3 V ±5%, housed in a 64-QFN 9×9 mm package.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any combination of output frequencies from any input frequency using fractional synthesis
• Features programmable jitter attenuation bandwidth ranging from 0.1 Hz to 4 kHz for optimized performance
• Supports hitless input clock switching between fractionally related clocks without phase offset propagation
• Includes in-circuit programmable non-volatile memory to ensure known frequency configuration upon power-up

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory preprogrammed configuration associated with the B00014 suffix against the required system specifications. Confirm that the QFN-64 package dimensions and thermal requirements align with the target PCB layout. Ensure compatibility with the serial interface protocol used by the host controller for initialization and monitoring.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when applications require up to ten differential or single-ended outputs with frequencies up to 350 MHz. The Si5345D variant supports integer and fractional synthesis modes suitable for complex clock tree generation. Verify that the input source matches the supported differential or LVCMOS ranges and that the system can accommodate the 1.8 V core and 3.3 V I/O supply rails.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5345 Rev D series, which integrates fourth-generation DSPLL technology. The Si5345D specifically denotes the 10-output variant within the 64-QFN package form factor. It is designed for high-performance timing applications requiring precise jitter attenuation and flexible frequency multiplication capabilities across multiple output channels.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Si5345B-Dxxxxx-GMR variants offer similar functionality but may differ in maximum output frequency limits or specific preprogrammed configurations. Cross-reference the exact frequency plan and output format requirements before substitution.