SI5345D-B06251-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5345D-B06251-GMR is a 10-channel, any-frequency jitter attenuator and clock multiplier from the Si5345 Rev D family. It features four inputs and ten outputs in a 64-QFN package. The device generates output frequencies ranging from 0.001 MHz to 350 MHz using integer and fractional synthesis modes. It supports differential input frequencies up to 750 MHz and LVCMOS inputs up to 250 MHz. Operating voltages include a core VDD of 1.8 V ±5% and VDDA of 3.3 V ±5%. The component operates within a temperature range of –40 °C to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Combines fourth-generation DSPLL and MultiSynth technologies for ultra-low jitter performance.
• Supports free-run, synchronous, and holdover modes with automatic or manual input switching.
• Features digitally programmable jitter attenuation bandwidth for application-level optimization.
• Includes in-circuit programmable non-volatile memory for known frequency configuration at power-up.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory preprogrammed configuration associated with the B06251 suffix against the official Skyworks ordering guide. Confirm that the required serial interface protocol (I2C or SPI) matches the system design. Ensure the external crystal specifications on XA/XB pins meet the recommended 48 MHz to 54 MHz range for optimal jitter performance.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when an output frequency limit of 350 MHz is sufficient, as higher frequency variants exist in the A and C series. The D suffix indicates specific frequency capabilities within the Rev D family. Use ClockBuilder Pro software to generate the necessary configuration data for the internal NVM. Verify compatibility with LVDS, LVPECL, LVCMOS, CML, and HCSL output requirements.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5345 Rev D family, which integrates DSPLL and MultiSynth technologies. The Si5345 variant specifically provides four inputs and ten outputs in a 9x9 mm 64-QFN package. It is designed for high-performance clock generation and jitter attenuation in telecommunications and networking infrastructure.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Factory preprogrammed devices require unique ordering part numbers assigned by Skyworks. Consult the official datasheet for potential cross-references within the Si5345/44/42 family based on input/output count and frequency range.