SI5346A-B06216-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5346A-B06216-GMR is a dual DSPLL jitter attenuator and clock generator manufactured by Skyworks Solutions. It integrates two independent DSPLLs within a 44-lead, 7x7 mm QFN package. The device supports four inputs and four outputs, enabling any-frequency conversion with typical jitter performance under 100 fs. Input frequency ranges include differential signals from 8 kHz to 750 MHz and LVCMOS from 8 kHz to 250 MHz. Output frequencies reach up to 720 MHz for differential formats and 250 MHz for LVCMOS. Operating voltage is 1.8 V ±5% for the core and 3.3 V ±5% for analog supplies.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Dual independent DSPLL architecture supporting flexible input-to-output crosspoint routing
• Ultra-low jitter attenuation capability with programmable loop bandwidth settings
• Automatic and hitless input clock switching with holdover mode support
• In-circuit programmability via I2C or SPI with non-volatile memory storage

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN Muxponders and Transponders
• 10/40/100G network line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• Broadcast video systems

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm package type and temperature range specifications. Ensure compatibility with ClockBuilder Pro software configurations if factory pre-programming is required. Confirm RoHS compliance status through official datasheets before finalizing procurement orders.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when dual independent timing paths are required in a compact form factor. The Si5346A variant supports output frequencies up to 720 MHz, suitable for high-speed serial applications. Consider the Si5347 if eight outputs are needed instead of four. Verify that the input signal formats match the supported differential or LVCMOS specifications.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the Si5346 family, which utilizes fourth-generation DSPLL technology. It serves as a lower-pin-count alternative to the Si5347, offering dual PLLs instead of quad PLLs while maintaining similar jitter performance characteristics. The device is designed for high-performance networking and telecommunications equipment requiring precise clock synchronization.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

The Si5347A-D-GM offers identical electrical performance but provides four DSPLLs and eight outputs in a larger 64-QFN package. Direct pin-compatible replacements are not available due to the different package footprints and pin counts between the Si5346 and Si5347 families.