SI5346A-C-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5346A-C-GMR is a dual DSPLL jitter attenuator in a 44-QFN package. It features two independent phase-locked loops with four inputs and four outputs. The device supports any-frequency conversion, accepting differential inputs from 8 kHz to 750 MHz and LVCMOS inputs up to 250 MHz. Output frequencies range from 100 Hz to 720 MHz for differential formats and up to 250 MHz for LVCMOS. It delivers ultra-low jitter performance of 95 fs rms (12 kHz–20 MHz). Operating voltage is 1.8 V ±5% for the core and 3.3 V ±5% for analog supplies. The component operates within a temperature range of –40 °C to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Dual independent DSPLLs enable flexible routing of any input clock to any output clock via a programmable crosspoint.
• Supports hitless and glitchless input switching, including ramped transitions for plesiochronous sources.
• Integrates automatic holdover and free-run modes to maintain timing stability during input signal loss.
• Includes comprehensive fault monitoring for Loss of Signal (LOS), Out-of-Frequency (OOF), and Loss of Lock (LOL).

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN Muxponders and Transponders
• 10/40/100G network line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• Broadcast video

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current datasheet to confirm package type and temperature grade. Confirm whether the 'R' suffix is required for tape-and-reel packaging versus tray options. Ensure compatibility with ClockBuilder Pro software versions for configuration generation. Check for any recent product change notifications or end-of-life notices affecting this specific revision.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when dual independent PLL paths are required within a compact footprint. Verify that the maximum output frequency requirements do not exceed 720 MHz for differential signals. Ensure the application can accommodate the 1.8 V core and 3.3 V analog supply rails. Consider the external crystal requirements on XA/XB pins for optimal jitter performance and holdover stability.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5346 Rev D family, which utilizes fourth-generation DSPLL technology. It serves as the dual-PLL counterpart to the quad-PLL Si5347 series. Both share similar functional architectures but differ in pin count and output capacity. The Si5346 is optimized for applications requiring two independent timing domains in a smaller 44-lead QFN package.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Si5346A-D-GM is a direct equivalent in the same family with identical specifications and package.