SI5346B-B05021-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5346B-B05021-GM is a dual DSPLL jitter attenuator from Skyworks Solutions, packaged in a 44-lead QFN. It supports any-frequency conversion with an ultra-low typical jitter of 95 fs rms (12 kHz to 20 MHz). The device accepts differential inputs from 8 kHz to 750 MHz and LVCMOS inputs up to 250 MHz. Outputs provide frequencies from 100 Hz to 350 MHz in differential formats or up to 250 MHz in LVCMOS. It operates on core voltages of 1.8 V and 3.3 V within a temperature range of -40 °C to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Dual independent DSPLLs enable flexible routing of any input clock to any output clock via a programmable crosspoint.
• Supports hitless input switching between frequency-locked sources and glitchless transitions for asynchronous inputs.
• Includes automatic holdover mode that preserves timing stability using historical frequency data during input loss.
• Features status monitoring for Loss of Signal (LOS), Out-of-Frequency (OOF), and Loss of Lock (LOL).

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN Muxponders and Transponders
• 10/40/100G network line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• Broadcast video

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm package type and temperature grade. Factory pre-programmed variants require unique numerical sequences assigned by ClockBuilder Pro software. Confirm availability through authorized distributors as supply levels may vary.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model for applications requiring two independent timing paths with low jitter performance. Ensure the required output frequency range does not exceed 350 MHz for differential outputs. Verify compatibility with available input signal types, including differential and LVCMOS formats, before finalizing the design.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5346 family, which serves as the dual DSPLL version of the Si5347 quad DSPLL series. Both share identical functional architectures but differ in pin count and output capacity. The Si5346 utilizes a compact 44-QFN package compared to the Si5347's 64-QFN form factor.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Si5346A-D-GM: Offers extended output frequency range up to 720 MHz.

Clock Generators, PLLs, Frequency Synthesizers FAQ

How does the device handle input clock failure?

The device automatically enters Holdover Mode when the selected input clock becomes invalid. It uses stored historical frequency data to maintain output stability until a valid input is restored.

What is the purpose of the Fastlock feature?

Fastlock allows the DSPLL to acquire lock faster by temporarily using a higher loop bandwidth during the acquisition process, after which it reverts to the configured lower bandwidth for optimal jitter performance.

Can the device switch between gapped input clocks?

Yes, the DSPLLs support locking to gapped clocks by averaging the missing cycles to produce a periodic non-gapped output clock with the average frequency.