SI5347A-B06307-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The Si5347A-B06307-GMR is a quad DSPLL jitter attenuator in a 64-QFN package. It features four independent phase-locked loops with any-frequency conversion capability. The device supports differential inputs from 8 kHz to 750 MHz and LVCMOS inputs up to 250 MHz. Output frequencies range from 100 Hz to 720 MHz for differential outputs and up to 250 MHz for LVCMOS. It achieves typical ultra-low jitter of 95 fs rms (12 kHz–20 MHz). Core voltage is 1.8 V ±5%, with independent output supplies at 3.3, 2.5, or 1.8 V. Operating temperature is –40 to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Four independent DSPLLs enable flexible routing of any input clock to any output via a programmable crosspoint.
• Supports hitless and glitchless input switching with automatic holdover and free-run modes for continuous operation.
• Integrates in-circuit programmable non-volatile memory for known power-up configurations without external components.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN Muxponders and Transponders
• 10/40/100G network line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix B06307 against Skyworks documentation to confirm factory pre-programmed configuration details. Ensure the GMR suffix matches the required tape and reel packaging specifications for automated assembly processes. Confirm RoHS-6 compliance and lead-free status as stated in the datasheet.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when four independent timing paths are required within a single component. The Si5347 variant provides eight outputs compared to the Si5346's four. Verify that the required output frequency range does not exceed 720 MHz for differential signals. Ensure the application supports the 64-QFN 9x9 mm package dimensions and thermal requirements.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the Si5347/46 Rev D family of dual and quad DSPLL jitter attenuators. It utilizes fourth-generation DSPLL technology for high integration. The 'A' grade indicates specific performance characteristics defined in the ordering guide. The device replaces older multi-chip solutions by integrating multiple PLLs and memory into one package.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Direct substitutes include other Si5347A variants with different output frequency ranges or pre-programming sequences. Cross-reference with Si5346 models if fewer outputs are acceptable. Verify pin compatibility and software configuration tools like ClockBuilder Pro for migration.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum differential output frequency?

The maximum differential output frequency is 720 MHz.

How does the device handle input clock failure?

It automatically enters Holdover Mode using stored historical frequency data to maintain output stability until a valid input is restored.

Can the device switch between inputs without glitches?

Yes, it supports glitchless input switching for frequencies up to ±500 ppm apart and hitless switching for frequency-locked inputs.