SI5369C-C-GQ

Clock Generators, PLLs, Frequency Synthesizers Overview

The Si5369-C-GQ is a jitter-attenuating precision clock multiplier utilizing third-generation DSPLL technology. It accepts four clock inputs from 2 kHz to 710 MHz and generates five outputs ranging from 2 kHz to 945 MHz, with select frequencies reaching 1.4 GHz. The device operates on a single 1.8 V, 2.5 V, or 3.3 V supply within an ambient temperature range of -40 °C to +85 °C. It features digitally programmable loop bandwidths between 4 Hz and 525 Hz, integrated loop filters, and supports I2C or SPI interfaces for configuration.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any frequency translation combination across the operating range using independent dividers for each input and output clock.
• Provides ultra-low jitter performance with generation as low as 300 fs rms in the 12 kHz–20 MHz band.
• Supports manual or automatically controlled hitless switching and phase build-out among four clock inputs.
• Includes SONET frame sync switching, regeneration capabilities, and support for ITU G.709 and custom FEC ratios.

Clock Generators, PLLs, Frequency Synthesizers Applications

• SONET/SDH OC-48/STM-16/OC-192/STM-64 line cards
• GbE/10GbE, 1/2/4/8/10G FC line cards
• ITU G.709 and custom FEC line cards
• Wireless repeaters and wireless backhaul systems
• Data converter clocking

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's official documentation to confirm package type, temperature grade, and lead-free status. Confirm that the required voltage levels match the device's operational specifications. Ensure compatibility with the intended control interface before procurement.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when sub 1 ps rms jitter performance is required for high-speed timing applications. Evaluate the maximum output frequency requirements against the speed grade limitations defined in the datasheet. Consider the power dissipation limits if multiple LVPECL or CMOS outputs are enabled simultaneously at 3.3 V operation.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The Si5369 belongs to Skyworks Solutions' Si53xx family of precision clock multipliers. It is designed to replace traditional solutions requiring external VCXOs and discrete loop filter components by integrating these functions into a highly integrated PLL solution.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Consult the official Skyworks Solutions replacement guide for verified substitute part numbers. Do not assume functional equivalence with other models in the family without verifying pinout and electrical specification compatibility.

Clock Generators, PLLs, Frequency Synthesizers FAQ

Does the Si5369 require external components for the loop filter?

No, the Si5369 eliminates the need for external VCXO and loop filter components through its integrated DSPLL technology.

What is the maximum output frequency supported by the CMOS format?

The maximum output frequency in CMOS format is limited to 212.5 MHz.

Can the device perform hitless switching between input clocks?

Yes, the Si5369 supports manual or automatically controlled hitless switching and phase build-out among its four clock inputs.