SI5381A-E-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The Si5381A-E-GM is a multi-DSPLL wireless jitter attenuator and clock multiplier designed for Baseband Unit (BBU) and Distribution Unit (DU) applications. It integrates four Digital Sample Phase-Locked Loops (DSPLLs) to replace discrete VCXO-based solutions. The device supports simultaneous Ethernet, CPRI, and general-purpose clocking with input frequencies ranging from 8 kHz to 750 MHz (differential) or 250 MHz (LVCMOS). Output capabilities include CPRI clocks up to 2.94912 GHz via DSPLL_B and other differential outputs up to 735 MHz. It features ultra-low RMS jitter of 72 fs typical at 122.88 MHz and complies with ITU-T G.8262 standards.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Integrates multiple DSPLLs to support simultaneous Ethernet, CPRI, and general-purpose clock generation in a single chip.
• Provides hitless, ramped, and glitchless input switching capabilities for seamless clock transitions.
• Includes automatic free-run and holdover modes with programmable history windows for robust operation during input loss.
• Offers status monitoring for Loss of Signal (LOS), Out-of-Frequency (OOF), and Loss of Lock (LOL).

Clock Generators, PLLs, Frequency Synthesizers Applications

• Wireless Infrastructure BBU and DU timing
• eCPRI Remote Radio Head (RRH) synchronization
• JESD204B Subclass 0 and 1 clocking for converters and FPGAs

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current datasheet to confirm package type, temperature range, and RoHS compliance status. Ensure that any custom factory pre-programmed requirements are defined using the ClockBuilder Pro utility prior to ordering, as standard parts require external configuration.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when replacing multiple discrete jitter attenuators with a unified solution for wireless infrastructure. Confirm that the required output frequencies fall within the DSPLL_B limit for CPRI or DSPLL_A/C/D limits for Ethernet. Verify compatibility with LVDS, LVPECL, LVCMOS, CML, or HSL output formats based on load requirements.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the Si5381/82 family of multi-DSPLL jitter attenuators. The Si5381 variant provides four DSPLLs, whereas the Si5382 offers two. Both share the same core architecture optimized for low-noise wireless clocking, utilizing a high-frequency DSPLL_B for CPRI and remaining DSPLLs for general-purpose tasks.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.