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— IC芯片 | 连接器 | 传感器 | 被动器件 —
The Infineon SLE 66C44PE is an 8/16-bit security controller manufactured in 0.22 µm CMOS technology, featuring the ECO2000 CPU core compatible with the SAB 8051 instruction set. It integrates 68 Kbytes of User ROM, 2 Kbytes XRAM, 256 bytes internal RAM, and a 4 Kbyte MicroSlim-EEPROM. The device includes a Dual Key Triple DES accelerator, a True Random Number Generator, and a CRC module. Operating voltages are available at 1.8 V, 3.0 V, or 5.0 V, with an internal clock frequency adjustable up to 33 MHz via PLL multiplication of an external clock ranging from 1 to 7.5 MHz.
Verify package availability as the component is offered as die (sawn/unsawn) or wire-bonded modules (M5). Confirm specific voltage ranges (1.8 V, 3.0 V, 5.0 V) and temperature grades (-25°C to +70°C or -25°C to +85°C) required for the target application. Contact sales representatives for detailed ordering information and qualification reports.
Select based on required operating voltage and temperature range. Ensure compatibility with existing SLE 66CxxxP masks if downward compatibility is needed. Consider the internal clock configuration (PLL x1 to x4) to balance performance against power consumption limits defined by GSM/UICC standards.
The SLE 66C44PE belongs to the improved 66PE series of security controllers. It serves as an evolution of the SLE 66P derivatives, offering increased memory capacity and enhanced security features while maintaining instruction set compatibility with standard SAB 8051 processors.
The datasheet indicates downward compatibility with existing SLE 66CxxxP products for existing masks without using new features. No specific alternative part numbers are listed in the provided documentation.
The internal clock frequency can be adjusted up to 33 MHz, achieved by multiplying the external clock frequency (1 to 7.5 MHz) using internal PLL dividers (x1, x2, x3, x4).
The Memory Management and Protection Unit separates the OS (system mode) from applications (user mode), allowing the OS to restrict peripheral access and define variable segments for secure application downloading and execution.
The chip includes a dedicated Dual Key Triple DES (DDES) accelerator and supports symmetric crypto algorithms in Electronic Code Book Mode. It also features a CRC module for checksum generation.