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The UNR32AEG0L is a Silicon NPN epitaxial planar type transistor designed for digital circuits. It functions as a single pre-biased BJT with an integrated bias resistor network, facilitating high-density mounting and equipment downsizing while contributing to low power consumption. Key electrical parameters include a collector-emitter breakdown voltage (Vceo) of 50 V, a maximum collector current (Ic) of 80 mA, and a transition frequency (fT) of 150 MHz. The device operates within a power dissipation limit of 100 mW, featuring a DC current gain (hFE) of at least 80 at Ic=5mA, Vce=10V, and a saturated collector-emitter voltage (Vce(sat)) of 250 mV max at Ib=300µA, Ic=10mA.
Verify the specific ordering suffix against official Panasonic Industry documentation to confirm exact pinout and packaging specifications. Confirm component availability status prior to procurement planning, as discrete semiconductor products may undergo lifecycle changes or discontinuation without immediate notice. Cross-reference part numbers with authorized distributors to ensure authenticity and traceability.
Select this component when a compact NPN pre-biased transistor is required for digital switching tasks. Ensure the 50 V collector-emitter voltage rating exceeds the maximum circuit operating voltage. Verify that the 80 mA collector current capability meets load requirements and that the 150 MHz transition frequency is sufficient for the intended signal speeds. Check thermal constraints against the 100 mW power dissipation limit.
This component belongs to the UNR series of silicon NPN epitaxial planar transistors manufactured by Panasonic Industry. These devices are specifically engineered for digital circuit applications where space efficiency and simplified biasing networks are critical. The series emphasizes low power consumption and suitability for automated surface mount processes.
Consult official Panasonic cross-reference lists for verified substitutes. Similar models in the UNR32A family may offer compatible electrical characteristics but require verification of pin configurations and specific parameter tolerances before implementation.