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The UPA800T-T1 is a dual NPN silicon high-frequency transistor housed in an S06 package measuring 2 mm x 1.25 mm. It contains two independent transistors (Q1 and Q2) optimized for low voltage and current operation. Key electrical characteristics include a collector-emitter voltage (VCEO) of 10 V, an emitter-base voltage (VEBO) of 1.5 V, and a maximum collector current of 35 mA. The device features a typical gain bandwidth product (fT) of 8.0 GHz at VCE = 3 V and IC = 5 mA. Power dissipation ratings are 110 mW per die and 200 mW total. Operating temperature ranges from -65°C to +150°C.
Verify the specific ordering suffix T1 when sourcing components to ensure correct tape and reel packaging containing 3000 units per reel. Confirm that the component matches the original California Eastern Laboratories specifications. Ensure compliance with absolute maximum ratings during handling and installation to prevent permanent damage.
Select this component for designs requiring compact RF amplification with minimal power consumption. The dual-transistor architecture allows for flexible circuit topologies including cascode configurations. Evaluate thermal management requirements against the 200 mW total power dissipation limit under expected operating conditions.
This part belongs to the UPA800T series manufactured by California Eastern Laboratories (CEL). The standard UPA800T variant is available without the T1 suffix, while the T1 designation specifically indicates the tape and reel packaging format. Both variants share identical electrical characteristics and pinouts.
No public confirmed substitute part numbers are documented in the provided datasheet. Verify compatibility carefully if considering alternative dual NPN RF transistors with similar package dimensions and frequency capabilities.
The UPA800T-T1 specifies the tape and reel packaging format containing 3000 units per reel, whereas the base UPA800T part number refers to the component itself without specifying the packaging method.
Yes, each transistor is independently mounted but can be easily configured for either dual transistor or cascode operation depending on the circuit design requirements.
The typical noise figure (NF) is 1.9 dB at 2 GHz when biased at VCE = 3 V and IC = 5 mA.