XCVM1802-2HSIVSVD1760

Soc System On Chip Overview

The AMD XCVM1802-2HSIVSVD1760 is a Versal Prime Series SoC FPGA in an FCBGA-1760 package. It integrates dual-core ARM Cortex-A72 and dual-core ARM Cortex-R5F processors with maximum clock frequencies of 600 MHz and 1.4 GHz, respectively. The device features L1 instruction caches of 2 x 48 kB and 2 x 32 kB, alongside L1 data caches of 2 x 32 kB and 2 x 32 kB. Designed for SMD/SMT installation, it operates within the Versal adaptive computing architecture.

Soc System On Chip Feature Summary

• Versal Prime Series adaptive SoC architecture
• Integrated dual-core ARM Cortex-A72 and dual-core ARM Cortex-R5F processing units
• FCBGA-1760 surface mount packaging

Soc System On Chip Applications

• Data center network acceleration
• Storage acceleration
• SmartNIC implementations
• 5G xHaul networking
• Nx100G Ethernet and OTN networking

Soc System On Chip Procurement Notes

Verify component authenticity through authorized AMD distributors or official channels. Confirm RoHS compliance status and specific manufacturing lot details against the datasheet. Ensure supply chain integrity by checking for recent Product Change Notifications (PCNs) that may affect specifications or availability.

Soc System On Chip Selection Notes

Select this model when Versal Prime performance meets system requirements. Compare core counts, cache sizes, and clock speeds against alternative part numbers like XCVM1802-1LSIVSVD1760 to ensure compatibility with specific design constraints and processing needs.

Soc System On Chip Part Context

This component belongs to the AMD Versal Prime series, targeting mid-range applications requiring high bandwidth DDR memory interfaces and low-latency inline acceleration. It complements other Versal devices by offering optimized compute engines for connectivity and storage workloads.

Soc System On Chip Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. Verify pinout and electrical compatibility before considering any cross-model alternatives.