ZL30112LDG1

Overview

The ZL30112LDG1 is a SLIC/CODEC Digital Phase-Locked Loop (DPLL) manufactured by Microchip Technology in a 32-pin QFN package. It synchronizes to input references of 8 kHz, 2.048 MHz, 8.192 MHz, or 19.44 MHz to generate precise timing signals. The device provides two clock outputs at 2.048 MHz and 8.192 MHz, along with an 8 kHz framing pulse. Operating on a nominal 3.3 V supply with a 1.8 V core voltage, it features a fixed DPLL bandwidth of 29 Hz and maintains less than 0.6 nsec peak-to-peak intrinsic jitter across all outputs.

Feature Summary

• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz, or 19.44 MHz input references
• Generates 2.048 MHz and 8.192 MHz clocks plus an 8 kHz framing pulse
• Fixed DPLL bandwidth of 29 Hz for network interface synchronization
• Less than 0.6 nsec peak-to-peak intrinsic jitter on output clocks

Applications

• Synchronizer for POTS SLIC/CODEC devices
• Rate conversion from NTR 8 kHz or GPON physical interface clocks to TDM clocks

Procurement Notes

Verify the component is the ZL30112LDG1 variant, which indicates lead-free matte tin plating and comes in trays with bake and drypack handling. Confirm the operating temperature range meets requirements of -40°C to +85°C. Ensure power sequencing adheres to specifications where the 3.3 V supply must not be powered after the 1.8 V core supply to prevent latch-up risks.

Selection Notes

Select this component when a fixed 29 Hz loop bandwidth is required for SLIC/CODEC synchronization. It supports master clock inputs via either a 20 MHz external oscillator or a crystal connected between OSCi and OSCo pins. The device requires LVCMOS compatible logic levels and includes automatic freerun mode entry upon reference failure to maintain system stability.

Part Context

The ZL30112LDG1 belongs to the ZL30112 family of SLIC/CODEC DPLLs originally developed by Zarlink Semiconductor. The 'LDG1' suffix denotes the specific package type (32-pin QFN), lead-free construction, and tray packaging configuration. This part is designed specifically for telecom applications requiring stable timing recovery from various standard digital hierarchy rates.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.