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The ZL30113LDF1 is a telecom rate conversion phase-locked loop (PLL) manufactured by Microchip Technology. It features one reference input and one CMOS output, supporting standard frequencies of 2.048 MHz, 8.192 MHz, and 65.536 MHz. The device includes fanout capability and generates one frame pulse output. Packaged in a 5 mm x 5 mm QFN, it provides less than 0.6 nspp intrinsic jitter on TDM clock outputs and incorporates status pins for lock indication and reference failure.
Verify the specific ordering suffix 'LDF1' against the manufacturer's current documentation to confirm package type and tape-and-reel specifications. Ensure compliance with RoHS standards as indicated in the product catalog. Confirm lead times directly with authorized distributors, as availability may vary based on production schedules.
Select this component when a single-input, single-output rate conversion PLL with standby mode is required. It is suitable for designs needing low intrinsic jitter (<0.6 nspp) and simple hardware control interfaces. Compare against the ZL30110 and ZL30112 if multiple outputs or different frequency ranges are necessary.
This part belongs to the ZL3011x series of telecom rate conversion PLLs from Microchip (formerly Zarlink). These devices are designed for volume designs in telecom, enterprise, and access equipment, offering integrated reference monitoring to ensure system reliability and compliance with industry standards.
The ZL30110 and ZL30112 are related parts within the same family. The ZL30110 offers nine CMOS outputs and multiple synthesizers, while the ZL30112 provides one CMOS output but lacks the standby capability found in the ZL30113. Verify pin compatibility and feature requirements before substitution.