ALD111933MAL

FET, MOSFET Arrays Overview

The ALD111933 is a high-precision monolithic dual N-Channel Enhancement Mode Matched Pair MOSFET Array manufactured using EPAD® CMOS technology. It features a precision matched +3.30V threshold voltage with a maximum offset voltage of 20mV, enabling nano-watt power operation. The device operates within a supply range of +3.0V to +10V, offering low input bias current and fast switching speeds. Key electrical parameters include a typical drain-source on resistance of 500Ω at VGS=7.3V, a forward transconductance of 1.4 mmho, and an input capacitance of 2.5pF. Available in 8-pin SOIC (SAL) and Plastic DIP (PAL) packages, it supports operating temperatures from 0°C to +70°C.

FET, MOSFET Arrays Feature Summary

• Factory-matched pair characteristics with tight parametric control for excellent temperature tracking
• Precision +3.30V gate threshold voltage enables ultra-low power nano-watt circuit designs
• High input impedance and low leakage currents suitable for sensitive analog signal processing
• Monolithic construction ensures differential thermal response and minimal offset voltage drift

FET, MOSFET Arrays Applications

• Precision current mirrors and sources
• Discrete voltage comparators and detectors
• Low power sample and hold circuits
• Analog switches and multiplexers
• Sensor interfaces and capacitive probes

FET, MOSFET Arrays Procurement Notes

Verify the specific package suffix when ordering: 'SAL' indicates the 8-pin SOIC package, while 'PAL' denotes the 8-pin Plastic DIP variant. Confirm that the lead-free (RoHS) designation aligns with project requirements. Ensure the operating environment remains within the specified 0°C to +70°C range. Check for ESD sensitivity precautions during handling and assembly to prevent damage to the high-impedance gate structures.

FET, MOSFET Arrays Selection Notes

Select this component for applications requiring precise matching between two N-Channel MOSFETs without external trimming. The fixed +3.30V threshold makes it ideal for low-voltage systems where standard MOSFETs would exhibit excessive leakage or poor matching. Consider the 500Ω on-resistance and 2.5pF input capacitance when designing for speed or drive strength limitations in nano-power environments.

FET, MOSFET Arrays Part Context

This device belongs to the ALD1108xx/ALD1109xx product family of EPAD® MOSFET arrays. It shares manufacturing technology with other threshold variants ranging from -3.50V to +3.50V. Unlike standard discrete MOSFETs, these devices are actively programmed for exceptional electrical characteristic matching and temperature coefficient tracking on a single monolithic chip.

FET, MOSFET Arrays Replacement Considerations

Direct replacements are limited due to the proprietary EPAD® programming. Standard dual MOSFETs lack the factory-matched 20mV offset specification. If substituting, verify that the alternative can achieve similar subthreshold leakage performance and threshold voltage stability under varying thermal conditions.

FET, MOSFET Arrays FAQ

What is the maximum offset voltage between the two matched MOSFETs?

The maximum offset voltage (VOS) between the two devices is specified as 20mV at IDS = 1µA.

How does the device behave in the subthreshold region?

In the subthreshold region, the drain current decreases exponentially with decreasing gate voltage, following a slope of approximately 116mV per decade of current decrease.

What is the typical input capacitance of the ALD111933?

The typical input capacitance (CISS) is 2.5 pF.