AT17C256-10PC

Overview

The AT17C256-10PC is a 256K-bit (262,144 x 1-bit) serial EEPROM designed for FPGA configuration. It operates at 5V nominal and supports commercial temperature ranges from 0°C to +70°C. The device utilizes a simple serial interface compatible with FPGA Master Serial Mode, featuring a DATA output, CLK input, and programmable RESET/OE polarity. It includes features such as low-power standby mode, write protection, and cascading capability via the CEO output for expanded memory configurations.

Feature Summary

• Designed specifically to store configuration programs for Field Programmable Gate Arrays (FPGAs)
• Supports in-system programming via a 2-wire serial bus
• Features programmable reset polarity and internal write-protection mechanisms
• Allows cascading of multiple devices to support higher-density FPGA arrays

Applications

• Configuration of Atmel AT6000 and AT40K FPGAs
• Configuration of Altera FLEX devices
• Configuration of Xilinx XC3000, XC4000, XC5200, and SPARTAN FPGAs
• Configuration of Lucent ORCA and Motorola MPA1000 FPGAs

Procurement Notes

Verify that the specific part number corresponds to the 5V commercial grade variant with an 8-pin PDIP package. Confirm the required operating temperature range aligns with the commercial specification (0°C to +70°C). Ensure compatibility with standard industry programmers or the Atmel ATDH2200E Programming Kit for initial configuration. Check datasheet specifications for absolute maximum ratings to prevent damage during handling.

Selection Notes

Select this component when a 256K-bit capacity is required for single or cascaded FPGA configuration. Choose the 5V version over the LV variant if the system supply voltage is strictly 5V ± 5%. Consider the 8-pin PDIP package for through-hole mounting requirements. Verify that the target FPGA supports the Master Serial Mode interface protocol defined in the device documentation.

Part Context

This component belongs to the AT17C/LV65/128/256 family of FPGA Configuration EEPROMs. These devices provide cost-effective memory solutions for loading configuration data into various FPGA architectures. The family includes 64K, 128K, and 256K density options available in both 5V and 3.3V versions, packaged in PDIP, SOIC, and PLCC formats.

Replacement Considerations

AT17LV256-10PC

FAQ

How is the reset polarity configured?

The reset polarity is programmable as either active High or active Low by writing to a special EEPROM byte using a standard programmer.

Can multiple AT17C256 devices be used together?

Yes, the device supports cascading via its CEO output, allowing connection to subsequent AT17C/LV128 or AT17C/LV256 devices for larger configuration memories.