AT17C512-10JC

Overview

The AT17C512-10JC is a 512-kilobit FPGA Configuration EEPROM manufactured by Microchip Technology (formerly Atmel). It provides non-volatile memory for programming Field Programmable Gate Arrays using a simple serial-access procedure. The device operates at a nominal 5V supply voltage and supports In-System Programming via a 2-wire bus. It features a system-friendly READY pin to indicate power stability and allows programmable reset polarity selection through four EEPROM bytes.

Feature Summary

• Designed specifically as a configurator memory for SRAM-based FPGAs
• Supports In-System Programming via a 2-wire serial bus interface
• Includes a READY pin that indicates valid power levels during startup
• Allows user-programmable logic polarity for the reset function

Applications

• Configuration of Xilinx XC3000, XC4000, XC5200, Spartan, and Virtex FPGAs
• Programming Altera FLEX and APEX devices
• Configuration of Atmel AT6000, AT40K, and AT94K devices
• Daisy-chaining multiple configuration memories for higher-density arrays

Procurement Notes

Verify the component manufacturer origin, as this part was originally produced by Atmel before its acquisition by Microchip Technology. Confirm the package type matches the required footprint, as the 'JC' suffix denotes a 20-lead PLCC package. Ensure the operating temperature range aligns with commercial specifications if industrial ratings are not required.

Selection Notes

Select this component when a cost-effective, high-density serial EEPROM is needed for FPGA configuration. It serves as a drop-in replacement for older PROM technologies like the XC17 series. Consider the AT17LV512 variant if the design requires a 3.3V supply voltage instead of the standard 5V operation provided by the AT17C series.

Part Context

This device belongs to the AT17 Series of high-density FPGA Configurators. It is designed to store configuration programs for various FPGA families. The series supports cascading capabilities to expand memory capacity beyond single-device limits. It utilizes a low-power CMOS EEPROM process and offers compatibility with industry-standard programmers.

Replacement Considerations

AT17LV512-10JC (3.3V version)

FAQ

How does the READY pin function during system initialization?

The READY pin is an open-collector output that is driven Low during the power-up reset cycle. It releases (tri-states) when the power-up is complete, signaling to the FPGA that the power level is stable.

Can the reset polarity be changed after manufacturing?

Yes, the user can program the reset polarity to be either active High or active Low by writing specific values to four EEPROM bytes during the programming phase.

What is the purpose of the CEO pin in a multi-device setup?

The Chip Enable Output (CEO) goes Low when the address counter reaches its maximum value. This signal enables the Chip Enable (CE) input of the next configurator in a daisy-chain sequence.