AT17F32-30BJU

Overview

The AT17F32-30BJU is a 32-Mbit In-System Programmable Configuration PROM packaged in a 44-lead PLCC. It operates at a nominal 3.3V supply voltage with 5V tolerant I/O pins and supports serial download speeds up to 33 MHz. The device features an industrial operating temperature range of -40°C to +85°C, low-power standby mode consuming less than 1 mA, and typical endurance of 10,000 write cycles.

Feature Summary

• Designed for storing configuration programs for Field Programmable Gate Arrays (FPGAs) via simple serial-access procedures.
• Supports In-System Programming (ISP) using a 2-wire bus interface and emulates Atmel’s AT24CXXX Serial EEPROMs.
• Capable of holding four bit stream files through page select inputs, allowing simple system reconfiguration from a single device.
• Features cascadable read-back capability to support additional configurations or higher-density FPGA arrays.

Applications

• Configuration memory for SRAM-based FPGAs such as Altera FLEX, APEX, Stratix, Lattice ORCA, Xilinx Spartan, and Virtex devices.
• Field Programmable Gate Array (FPGA) configurators requiring cost-effective, easy-to-use storage solutions.
• Systems requiring multiple configuration bitstreams stored within a single memory device.

Procurement Notes

Verify the ordering code AT17F32-30BJU corresponds to the 44-lead PLCC package with Lead and Halide Free (LHF) compliance and Industrial temperature range (-40°C to +85°C). Confirm that the supplier provides documentation consistent with the Microchip/Atmel datasheet specifications for this specific variant.

Selection Notes

Select this component when designing systems requiring 32-Mbit capacity for FPGA configuration with 3.3V logic levels. Ensure the design accommodates the 44-lead PLCC footprint and utilizes the 2-wire serial programming interface if ISP capabilities are required. Verify compatibility with the target FPGA's master serial mode requirements.

Part Context

This device belongs to the AT17F Series of In-System Programmable Configuration PROMs. These configurators provide a solution for loading configuration programs into FPGAs automatically upon power-up or on command. The series is designed for compatibility with various major FPGA families and supports daisy-chaining for larger memory needs.

Replacement Considerations

Compatible with Atmel AT40K and AT94K devices. Also compatible with Altera FLEX, APEX, Stratix, Lattice Semiconductor ORCA, Xilinx Spartan, and Virtex FPGAs.

FAQ

How does the device handle multiple configuration bitstreams?

By setting the PAGE_EN input high, the address space is partitioned into four equal pages. The PAGESEL inputs determine which page is targeted during a serial configuration download.

What is the function of the CEO pin in a cascaded setup?

In a daisy chain, the CEO output goes Low when the internal address counter reaches its maximum value. This signal drives the CE input of the next configurator in the chain, enabling it to output data after the previous device finishes.

How is the device programmed?

Programming is performed via a 2-wire serial bus by bringing the SER_EN input Low. Super voltages required for programming are generated internally, allowing programming at the VCC supply voltage only.