AT17LV65-10PI

Configuration PROMs For FPGAs Overview

The AT17LV65-10PI is a 64-Kbit serial EEPROM configurator designed for FPGA configuration. It supports both 3.3V and 5.0V operating voltages and features in-system programmability via a two-wire bus. The device operates within an industrial temperature range of -40°C to +85°C and is housed in an 8-lead PDIP package.

Configuration PROMs For FPGAs Feature Summary

• Supports in-system programming via a two-wire serial bus interface
• Compatible with SRAM-based FPGAs including Xilinx, Altera, Atmel, and Lattice devices
• Allows user-programmable reset polarity configuration
• Provides low-power standby mode operation

Configuration PROMs For FPGAs Applications

• Configuration memory for Field Programmable Gate Arrays (FPGAs)
• In-system programming of FPGA configuration data
• Industrial applications requiring wide temperature operation

Configuration PROMs For FPGAs Procurement Notes

Verify the specific ordering suffix 'PI' corresponds to the 8-lead PDIP package and Industrial temperature range (-40°C to +85°C). Confirm that the 64-Kbit capacity matches the design requirements, as this part belongs to a series with varying densities. Ensure compatibility with the target FPGA's master serial mode requirements.

Configuration PROMs For FPGAs Selection Notes

Select this component when a 64-Kbit configuration memory is required for SRAM-based FPGAs. The Industrial temperature rating makes it suitable for harsh environments. Consider alternative packages like SOIC or LAP if space constraints differ, noting that pinouts may vary between density groups within the series.

Configuration PROMs For FPGAs Part Context

This device is part of the AT17LV series of FPGA Configuration EEPROMs manufactured by Microchip Technology (formerly Atmel). These configurators provide a cost-effective solution for storing configuration programs for various FPGA families. The series supports multiple memory sizes and voltage levels to accommodate diverse system designs.

Configuration PROMs For FPGAs Replacement Considerations

AT17LV65-10PC (Commercial Temperature Range)

Configuration PROMs For FPGAs FAQ

Is the CEO feature available on the AT17LV65?

No, the Chip Enable Output (CEO) feature is not available on the AT17LV65 device, which prevents it from being used in cascaded configurations.

How is the reset polarity configured?

The reset polarity can be programmed by the user to be either active high or active low using four specific EEPROM bytes during the programming process.