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The C3M0075120J is a third-generation Silicon Carbide (SiC) MOSFET from Wolfspeed, packaged in a TO-263-7L configuration. It features an N-channel enhancement mode design with a maximum drain-source voltage of 1200 V and a typical on-resistance of 75 mΩ at 25°C. The device supports a continuous drain current of 30 A and operates within a junction temperature range of -55°C to +150°C. Key electrical characteristics include a total gate charge of 48 nC and a reverse recovery charge of 109 nC for the intrinsic diode.
Verify the specific ordering suffix 'J' corresponds to the TO-263-7L package variant when sourcing components. Confirm RoHS compliance status and REACh SVHC declarations directly with the manufacturer or authorized distributors prior to procurement. Ensure that the supply chain provides valid traceability documentation consistent with Wolfspeed quality standards.
Select this component for designs requiring robust performance in high-voltage environments up to 1200 V. The TO-263-7L package facilitates surface-mount integration while maintaining thermal efficiency through the tab connection. Consider the 75 mΩ on-resistance and associated switching losses when evaluating system-level efficiency targets and cooling requirements.
This part belongs to the C3M family of silicon carbide power MOSFETs manufactured by Wolfspeed. The product line utilizes advanced third-generation SiC technology to deliver superior power density compared to traditional silicon devices. The TO-263-7L package is specifically designed to support high-frequency switching applications with reduced electromagnetic interference.
Direct replacements must match the 1200 V rating, TO-263-7L package, and comparable RDS(on) specifications. Verify compatibility with existing gate drive voltages and thermal management solutions before substituting with alternative manufacturers' parts.
The datasheet specifies a recommended turn-on gate voltage of 15 V with a ±5% regulation tolerance.
The TO-263-7L package includes a dedicated Kelvin source pin (Pin 2) separate from the power source pins, which minimizes gate loop inductance and reduces switching noise.