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Product Detailed Parameters
- Description：MOSFET P-CH 30V 2.4A DIE
- Series：-
- Mfr：Central Semiconductor Corp
- Package：Tray
- FET Type：P-Channel
- Technology：MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss)：30 V
- Current - Continuous Drain (Id) @ 25°C：2.4A (Ta)
- Drive Voltage (Max Rds On, Min Rds On)：2.5V, 4.5V
- Rds On (Max) @ Id, Vgs：91mOhm @ 1.2A, 4.5V
- Vgs(th) (Max) @ Id：1.4V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs：9.6 nC @ 5 V
- Vgs (Max)：12V
- Input Capacitance (Ciss) (Max) @ Vds：800 pF @ 10 V
- FET Feature：-
- Power Dissipation (Max)：-
- Operating Temperature：-55°C ~ 150°C (TJ)
- Grade：-
- Qualification：-
- Mounting Type：Surface Mount
- Supplier Device Package：Die
- Package / Case：Die
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Overview
The CP798X-CPDM302PH is a silicon P-Channel MOSFET die designed for high-speed pulsed amplifier and driver applications. It features a drain-source voltage of 30 V, continuous drain current of 2.4 A, and maximum pulsed drain current of 9.6 A. The device operates within a junction temperature range of -55 to +150 °C. Electrical characteristics include a gate-source threshold voltage of 0.7 to 1.4 V, on-resistance of 0.091 Ω at 4.5 V gate drive, and total gate charge of 9.6 nC. Physical dimensions include a die size of 37.8 x 26 MILS and thickness of 5.5 MILS.
Feature Summary
- Engineered as a bare die for integration into custom packaging or substrate designs.
- Optimized for high-speed pulsed amplifier and driver applications.
- Features enhanced-mode P-Channel silicon construction.
Applications
- High speed pulsed amplifier circuits
- Driver applications requiring bare die integration
Procurement Notes
Verify the specific ordering suffix required for your application, such as WN for unsawn wafers, WR for sawn wafers on plastic rings, CT for singulated die in trays, or CM for visually inspected singulated die. Confirm plating requirements by adding TIN/LEAD or PBFREE suffixes if necessary. Contact Central Semiconductor directly for special orders like metal frame mounting.
Selection Notes
Select this component when a discrete packaged MOSFET is not suitable for the form factor or thermal management needs of the design. Ensure the layout accommodates the specific bonding pad sizes: Gate (7.3 x 7.3 MILS) and Source (34 x 22.2 MILS). Verify that the application can handle the specified electrical limits, including the 30 V breakdown and 2.4 A steady-state current.
Part Context
This part is a bare die version of the CPDM302PH product line from Central Semiconductor Corp. Unlike standard surface-mount packages, this component requires manual or automated die attachment and wire bonding during assembly. It is intended for manufacturers creating custom power modules or integrating semiconductors directly onto substrates.
Replacement Considerations
No public confirmed substitute part numbers are available in the documentation.
FAQ
What are the physical dimensions of the die?
The die size is 37.8 x 26 MILS with a thickness of 5.5 MILS.
How is the gate bonding pad sized?
The gate bonding pad measures 7.3 x 7.3 MILS.
What packing options are available for this die?
Options include unsawn wafers (WN), sawn wafers on plastic rings (WR), singulated die in waffle packs (CT), and visually inspected singulated die (CM).
