LTC6945IUFD#PBF

Clock Generators, PLLs, Frequency Synthesizers Overview

The LTC6945IUFD#PBF is an ultralow noise and spurious integer-N synthesizer with an integrated VCO output divider, operating from 350MHz to 6GHz. It features a high-performance phase-locked loop (PLL) architecture including a reference divider, phase-frequency detector with lock indicator, charge pump, and integer feedback divider. The device provides a buffered, programmable VCO output divider ranging from 1 to 6, delivering user-programmable output power between –6dBm and 3dBm. A low-noise reference buffer outputs a square wave directly into 50Ω from 10MHz to 250MHz. All settings are managed via an SPI-compatible serial port.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Ultralow noise performance: –226dBc/Hz normalized in-band phase noise floor and –274dBc/Hz normalized 1/f noise
• Integrated VCO output divider with range of 1 through 6 and user-programmable output power from –6dBm to 3dBm
• Low noise reference buffer providing typical 0dBm square wave output into 50Ω from 10MHz to 250MHz
• Charge pump with selectable high and low voltage clamps for VCO monitoring and V+/2 bias capability

Clock Generators, PLLs, Frequency Synthesizers Applications

• Wireless Base Stations (LTE, WiMAX, W-CDMA, PCS)
• Broadband Wireless Access
• Microwave Data Links
• Military and Secure Radio
• Test and Measurement

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix #PBF indicates lead-free finish and RoHS compliance as per manufacturer documentation. Confirm package details match the 28-lead (4mm × 5mm) plastic QFN specification. Ensure thermal management requirements are met by soldering the exposed pad directly to the PCB ground plane with thermal vias.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select based on required output frequency range up to 6GHz and phase noise specifications. Consider the charge pump current range of 250µA to 11.2mA for loop filter design. Verify supply voltage compatibility within the 3.15V to 5.25V range for VCP+ and 3.15V to 3.45V for other supplies. Use PLLWizard software for optimal configuration.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The LTC6945 is part of the Linear Technology (now Analog Devices) portfolio of high-performance analog integrated circuits. It is designed for applications requiring precise frequency synthesis with minimal jitter and spurious content. The device integrates key PLL components to simplify system design while maintaining superior RF performance metrics.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Consult Analog Devices marketing for parts specified with wider operating temperature ranges or non-standard lead-based finishes. Evaluate alternative models within the same family if specific pinout or electrical parameter variations are required for the application.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum output frequency of the LTC6945?

The maximum output frequency is 6GHz.

How is the output power controlled?

The output power is user-programmable via the serial port, ranging from –6dBm to 3dBm.

Can the reference buffer be disabled?

Yes, the reference buffer can be disabled through software control using the PDREFO bit in the serial port Power register.

What is the function of the STAT pin?

The STAT pin provides a configurable status output that is a logical OR combination of UNLOCK, LOCK, THI, and TLO status bits.