LTC6955IUKG-1#TRPBF

Clock Generators, PLLs, Frequency Synthesizers Overview

The LTC6955IUKG-1#TRPBF is an ultralow jitter, 7.5GHz, 11-output fanout buffer family member manufactured by Analog Devices Inc. It features a 52-lead (7mm × 8mm) plastic QFN package with an exposed ground pad. The device provides eleven CML outputs capable of running from DC to 7.5GHz. Unlike the standard LTC6955, the -1 variant replaces one output buffer with a divide-by-2 frequency divider on OUT10, allowing it to drive Analog Devices’ LTC6952 or LTC6953 for JESD204B Subclass 1 SYSREF signal generation. Additive output jitter is approximately 45fs RMS using the ADC SNR method and less than 5fs RMS in the 12kHz to 20MHz integration bandwidth at 7.5GHz.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Ultralow additive output jitter: ~45fs RMS (ADC SNR Method) and <5fs RMS (12kHz–20MHz BW at 7.5GHz)
• Eleven low-noise CML outputs; OUT10 is a divide-by-2 frequency divider
• Four-pin parallel control port enables configurable output setups (3 to 11 active outputs) and polarity inversion
• Operating junction temperature range of –40°C to 125°C

Clock Generators, PLLs, Frequency Synthesizers Applications

• High-performance data converter clocking
• JESD204B/C Subclass 1 SYSREF signal generation paired with device clocks
• SONET, Fibre Channel, and GigE clock distribution
• Low skew and jitter clock and data fanout in wireless and wired communications

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix #TRPBF indicates tape and reel packaging. Confirm the -1 designation matches the required divide-by-2 functionality on OUT10. Ensure the I grade specification aligns with the required –40°C to 125°C operating junction temperature range. Cross-reference the 52-lead QFN footprint with PCB layout guidelines for thermal and electrical performance.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select the LTC6955IUKG-1#TRPBF when a divide-by-2 output is required for SYSREF synchronization with LTC6952/LTC6953 devices. Choose the standard LTC6955IUKG#TRPBF if all eleven outputs must be undivided buffers. Consider the FILT pin configuration based on input slew rate; enable filtering for inputs below 2V/ns to improve phase noise. Ensure supply voltages remain within the 3.15V to 3.45V range for optimal performance.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The LTC6955IUKG-1#TRPBF belongs to the LTC6955 family of ultralow jitter fanout buffers. It shares the same core architecture as the LTC6955 but integrates a frequency divider on the OUT10 channel. This variation is specifically designed to simplify system designs requiring precise timing alignment between high-speed clocks and SYSREF signals in multi-chip data acquisition systems.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation.