M2020-11-625.0000T

Clock Generators, PLLs, Frequency Synthesizers Overview

The M2020-11-625.0000T is a VCSO-based clock jitter attenuator PLL manufactured by Integrated Circuit Systems, Inc., now part of Renesas Electronics. It integrates a SAW delay line to provide low phase noise and jitter attenuation for optical network systems supporting 2.5-10 Gb/s data rates. The device operates on a single 3.3V supply within a 9x9 mm SMT package. It accepts differential LVDS/LVPECL or single-ended LVCMOS/LVTTL reference inputs and provides dual differential LVPECL outputs. Key features include pin-selectable dividers, narrow bandwidth control, and optional hitless switching with phase build-out for SONET/SDH compliance.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Integrated SAW delay line providing typical output jitter of < 0.5ps rms (12kHz to 20MHz offset range).
• Supports input frequencies from 10 MHz to 700 MHz and generates output frequencies from 15 MHz to 700 MHz.
• Features dual differential LVPECL clock outputs with TriState capability for manufacturing in-circuit testing.
• Includes Loss of Lock (LOL) indicator and Narrow Bandwidth (NBW) control pin for loop tuning.

Clock Generators, PLLs, Frequency Synthesizers Applications

• Generating transmit reference clocks for optical network systems.
• Jitter attenuation for stratum reference clocks.
• Loop timing mode applications requiring recovered clock synchronization.

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current product lifecycle status. Confirm that the required VCSO center frequency matches the fixed internal oscillator specification defined at the time of order. Ensure external loop filter components are selected according to the provided simulator tool guidelines to achieve target bandwidth and damping factors.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select the appropriate divider settings (Mfin, M, R, P) based on the desired input reference frequency and output clock requirements. Choose between commercial (0°C to +70°C) or industrial (-40°C to +85°C) temperature grades as needed. Consider the optional Hitless Switching and Phase Build-out features if SONET/SDH MTIE/TDEV compliance during reference reselection is required.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the M2020/21 family of VCSO-based clock PLLs. The M2020 variant typically includes Hitless Switching options, while the M2021 may offer different configuration capabilities. These devices are designed to replace multiple crystals and oscillators, reducing board space and cost in high-performance networking equipment.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation. When replacing this component, ensure the new device supports the same VCSO center frequency, output voltage levels (LVPECL), and package dimensions (9x9 mm SMT). Verify compatibility with existing divider configurations and loop filter designs.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the function of the NBW pin?

The NBW pin controls the PLL loop bandwidth. Asserting it (Logic 1) enables narrow bandwidth mode with an internal resistor of 2100kΩ, while de-asserting it (Logic 0) sets wide bandwidth mode with 100kΩ.

How does the device handle unused outputs?

Unused outputs should be left unconnected (floating) to minimize output switching current and reduce noise modulation of the VCSO. The TriState feature can also be used to disconnect the driver.

What is the purpose of the LOL pin?

The Loss of Lock (LOL) pin indicates when the PLL is not tracking the input reference. It goes high (Logic 1) if the phase error exceeds 4 ns and returns low (Logic 0) when the error is less than 2 ns.