MC10EP139DT

Clock Generators, PLLs, Frequency Synthesizers Overview

The MC10EP139DT is a low skew clock generation chip from the onsemi 10EP series, housed in a TSSOP-20 Wide Body (CASE 948E) package. It functions as a ÷2/4 and ÷4/5/6 divider with synchronous internal dividers for precise output edge alignment. The device supports PECL mode (VCC = 3.0 V to 5.5 V, VEE = 0 V) and NECL mode (VCC = 0 V, VEE = −3.0 V to −5.5 V). Key electrical parameters include a maximum frequency exceeding 1.0 GHz, typical power supply current of 82 mA at 25°C, and output-to-output skew of 50 ps. It features a master reset input for synchronization and an internally generated VBB reference voltage.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Low skew design with 50 ps typical output-to-output skew and synchronous enable/disable logic.
• Configurable division ratios: ÷2 or ÷4 for Q0/Q1 outputs; ÷4, ÷5, or ÷6 for Q2/Q3 outputs via DIVSEL inputs.
• Supports both PECL (3.0 V–5.5 V) and NECL (−3.0 V to −5.5 V) operating modes.
• Includes safety clamps on inputs, open input default state, and a VBB pin for single-ended reference.

Clock Generators, PLLs, Frequency Synthesizers Applications

• Low skew clock generation in high-speed digital systems.
• Clock distribution networks requiring synchronized multiple output edges.
• Systems utilizing ECL, PECL, or NECL logic families.

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the ordering suffix 'DT' corresponds to the TSSOP-20 WB package (CASE 948E) and confirm RoHS compliance status ('G' suffix indicates Pb-Free). Ensure all VCC and VEE pins are externally connected to power supplies for proper operation. Check moisture sensitivity levels, which vary by package type, and adhere to recommended soldering profiles.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when precise alignment between divided clock outputs is required. The 10EP series lacks temperature compensation compared to the 100EP series; verify if thermal stability requirements necessitate the MC100EP139 variant. Ensure the application supports differential ECL inputs or utilizes the VBB pin for single-ended conversion. Confirm power supply constraints align with the specified PECL or NECL ranges.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The MC10EP139 belongs to the 10EP family of ECL clock generators. It shares functional similarities with the MC100EP139, though the 100EP series includes temperature compensation. The 'DT' suffix specifically denotes the TSSOP-20 Wide Body package. Other available packages include SOIC-20 (DW) and QFN-20 (MN).

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

The MC100EP139DTG is a direct functional substitute within the same package, offering added temperature compensation. For package variations, the MC10EP139DWR2G provides the same function in a tape-and-reel SOIC-20 format.